Add the "jetway j7f[24]*" mainboard. As compared to the Via Epia CN, this
changes the superio to a Fintek F71805F as described at http://www.coreboot.org/Jetway_J7F2_Build_Tutorial It also creates the mainboard tree for this series of motherboards (Jetway J7F2 and J7F4). I've tested it with one motherboard (J7F2WE1G3), and I believe it works with the others, as the differences among them are mostly trivial (processor speed, chipset and quantity of LAN cards, audio chipset, etc.). A list of the relevant motherboards with specs can be found at http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16 The irq_tables.c is copied directly from the epia-cn, because the one generated by getpir with the factory BIOS did not work properly while the EPIA-CN one did. Minor changes on checkin to cope with moved romcc in latest revision. NOTE: This board is broken until the issue introduced in r3567 is resolved. Signed-off-by: Alex Mauer <hawke@hawkesnest.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Alex Mauer
Stefan Reinauer
parent
eb2b8a282c
commit
9196dd553d
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@ -0,0 +1,144 @@
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##
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## This file is part of the coreboot project.
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##
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||||
## Copyright (C) 2008 VIA Technologies, Inc.
|
||||
## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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||||
##
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||||
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
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else
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default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
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default ROM_SECTION_OFFSET = 0
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end
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default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
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default XIP_ROM_SIZE = 64 * 1024
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default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
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arch i386 end
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driver mainboard.o
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if HAVE_PIRQ_TABLE object irq_tables.o end
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_ACPI_TABLES
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object fadt.o
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object dsdt.o
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object acpi_tables.o
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end
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makerule ./failover.E
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
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action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
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action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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mainboardinit arch/i386/lib/cpu_reset.inc
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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dir /pc80
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config chip.h
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chip northbridge/via/cn700 # Northbridge
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # AGP Bridge
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device pci 0.1 on end # Error Reporting
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device pci 0.2 on end # Host Bus Control
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device pci 0.3 on end # Memory Controller
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device pci 0.4 on end # Power Management
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device pci 0.7 on end # V-Link Controller
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device pci 1.0 on end # PCI Bridge
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chip southbridge/via/vt8237r # Southbridge
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# Enable both IDE channels.
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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# Both cables are 40pin.
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register "ide0_80pin_cable" = "0"
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register "ide1_80pin_cable" = "0"
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device pci f.0 on end # IDE
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register "fn_ctrl_lo" = "0x80"
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register "fn_ctrl_hi" = "0x1d"
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device pci 10.0 on end # OHCI
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device pci 10.1 on end # OHCI
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device pci 10.2 on end # OHCI
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device pci 10.3 on end # OHCI
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device pci 10.4 on end # EHCI
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device pci 10.5 on end # UDCI
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device pci 11.0 on # Southbridge LPC
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chip superio/fintek/f71805f # Super I/O
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
|
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drq 0x74 = 2
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end
|
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device pnp 2e.1 on # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
|
||||
device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # COM2
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io 0x60 = 0x2f8
|
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irq 0x70 = 3
|
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end
|
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device pnp 2e.b on # HWM
|
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io 0x60 = 0xec00
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end
|
||||
end
|
||||
end
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device pci 11.5 on end # AC'97 audio
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# device pci 11.6 off end # AC'97 Modem
|
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device pci 12.0 on end # Ethernet
|
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end
|
||||
end
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device apic_cluster 0 on # APIC cluster
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chip cpu/via/model_c7 # VIA C7
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device apic 0 on end # APIC
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end
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||||
end
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||||
end
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@ -0,0 +1,108 @@
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##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 VIA Technologies, Inc.
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||||
## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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||||
##
|
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|
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HAVE_OPTION_TABLE
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uses USE_OPTION_TABLE
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uses CONFIG_ROM_PAYLOAD
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uses IRQ_SLOT_COUNT
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uses MAINBOARD
|
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uses MAINBOARD_VENDOR
|
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uses MAINBOARD_PART_NUMBER
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uses COREBOOT_EXTRA_VERSION
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uses ARCH
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uses FALLBACK_SIZE
|
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uses STACK_SIZE
|
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uses HEAP_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
|
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uses ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD_START
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
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uses PAYLOAD_SIZE
|
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uses _ROMBASE
|
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uses _RAMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses HAVE_MP_TABLE
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uses HAVE_ACPI_TABLES
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses CONFIG_PCI_ROM_RUN
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_MAX_PCI_BUSES
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uses TTYS0_BAUD
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uses CONFIG_CHIP_NAME
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uses CONFIG_VIDEO_MB
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uses CONFIG_IOAPIC
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default ROM_SIZE = 512 * 1024
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default CONFIG_IOAPIC = 0
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default CONFIG_VIDEO_MB = 32
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default CONFIG_CONSOLE_SERIAL8250 = 1
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default CONFIG_PCI_ROM_RUN = 0
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default CONFIG_CONSOLE_VGA = 0
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default CONFIG_CHIP_NAME = 1
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default HAVE_FALLBACK_BOOT = 1
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default HAVE_MP_TABLE = 0
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default CONFIG_UDELAY_TSC = 1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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default HAVE_HARD_RESET = 0
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default HAVE_PIRQ_TABLE = 1
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default IRQ_SLOT_COUNT = 10
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default HAVE_ACPI_TABLES = 0
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default HAVE_OPTION_TABLE = 1
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default ROM_IMAGE_SIZE = 64 * 1024
|
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default FALLBACK_SIZE = ROM_SIZE
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default USE_FALLBACK_IMAGE = 1
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default STACK_SIZE = 8 * 1024
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default HEAP_SIZE = 16 * 1024
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||||
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||
default USE_OPTION_TABLE = 0
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||||
default _RAMBASE = 0x00004000
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default CONFIG_ROM_PAYLOAD = 1
|
||||
default CROSS_COMPILE = ""
|
||||
default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
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||||
default HOSTCC = "gcc"
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||||
|
||||
##
|
||||
## Set this to the max PCI bus number you would ever use for PCI config I/O.
|
||||
## Setting this number very high will make pci_locate_device() take a long
|
||||
## time when it can't find a device.
|
||||
##
|
||||
default CONFIG_MAX_PCI_BUSES = 3
|
||||
|
||||
end
|
||||
|
||||
|
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@ -0,0 +1,124 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 VIA Technologies, Inc.
|
||||
* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY 1
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <arch/hlt.h>
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include "ram/ramtest.c"
|
||||
#include "northbridge/via/cn700/raminit.h"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "pc80/udelay_io.c"
|
||||
#include "lib/delay.c"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
|
||||
#include "southbridge/via/vt8235/vt8235_early_serial.c"
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/via/cn700/raminit.c"
|
||||
|
||||
static void enable_mainboard_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
u8 reg;
|
||||
|
||||
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
|
||||
if (dev == PCI_DEV_INVALID)
|
||||
die("Southbridge not found!!!\n");
|
||||
|
||||
/* bit=0 means enable function (per CX700 datasheet)
|
||||
* 5 16.1 USB 2
|
||||
* 4 16.0 USB 1
|
||||
* 3 15.0 SATA and PATA
|
||||
* 2 16.2 USB 3
|
||||
* 1 16.4 USB EHCI
|
||||
*/
|
||||
pci_write_config8(dev, 0x50, 0x80);
|
||||
|
||||
/* bit=1 means enable internal function (per CX700 datasheet)
|
||||
* 3 Internal RTC
|
||||
* 2 Internal PS2 Mouse
|
||||
* 1 Internal KBC Configuration
|
||||
* 0 Internal Keyboard Controller
|
||||
*/
|
||||
pci_write_config8(dev, 0x51, 0x1d);
|
||||
}
|
||||
|
||||
static const struct mem_controller ctrl = {
|
||||
.d0f0 = 0x0000,
|
||||
.d0f2 = 0x2000,
|
||||
.d0f3 = 0x3000,
|
||||
.d0f4 = 0x4000,
|
||||
.d0f7 = 0x7000,
|
||||
.d1f0 = 0x8000,
|
||||
.channel0 = { 0x50 },
|
||||
};
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
unsigned long x;
|
||||
device_t dev;
|
||||
|
||||
/* Enable multifunction for northbridge. */
|
||||
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
|
||||
|
||||
enable_vt8235_serial();
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
print_spew("In auto.c:main()\r\n");
|
||||
|
||||
enable_smbus();
|
||||
smbus_fixup(&ctrl);
|
||||
|
||||
if (bist == 0) {
|
||||
print_debug("doing early_mtrr\r\n");
|
||||
early_mtrr_init();
|
||||
}
|
||||
|
||||
/* Halt if there was a built-in self test failure. */
|
||||
report_bist_failure(bist);
|
||||
|
||||
print_debug("Enabling mainboard devices\r\n");
|
||||
enable_mainboard_devices();
|
||||
|
||||
ddr_ram_setup(&ctrl);
|
||||
|
||||
/* ram_check(0, 640 * 1024); */
|
||||
|
||||
print_spew("Leaving auto.c:main()\r\n");
|
||||
}
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 VIA Technologies, Inc.
|
||||
* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
extern struct chip_operations mainboard_jetway_j7f24_ops;
|
||||
|
||||
struct mainboard_jetway_j7f24_config {
|
||||
int nothing;
|
||||
};
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
1008 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 1007 1008
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 VIA Technologies, Inc.
|
||||
* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE,
|
||||
PIRQ_VERSION,
|
||||
32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
|
||||
0x00, /* Interrupt router bus */
|
||||
(0x11 << 3) | 0x0, /* Interrupt router device */
|
||||
0x828, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1106, /* Vendor */
|
||||
0x596, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x3e, /* Checksum */
|
||||
{
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
|
||||
{0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
|
||||
{0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
|
||||
{0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
|
||||
{0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
|
||||
{0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
|
||||
{0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
|
||||
{0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
|
||||
{0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
|
||||
{0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 VIA Technologies, Inc.
|
||||
* (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations mainboard_jetway_j7f24_ops = {
|
||||
CHIP_NAME("Jetway J7F[24]* Mainboard")
|
||||
};
|
||||
Loading…
Reference in New Issue