GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mainboard/asus/kgpe-d16: Add nvram option to enable/disable IEEE 1394 

Change-Id: I4f0f6c1cb1fad5b65f196dc6b443252a0ecc70a1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11947
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Timothy Pearson 2015-08-11 18:38:06 -05:00 committed by Nico Huber
parent 8f5053c626
commit 919d9ba633
3 changed files with 19 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/asus/kgpe-d16/cmos.default
View File

@ -12,5 +12,6 @@ ecc_scrub_rate = 1.28us
interleave_chip_selects = Enable
interleave_nodes = Disable
interleave_memory_channels = Enable
ieee1394_controller = Enable
power_on_after_fail = On
boot_option = Fallback

1
src/mainboard/asus/kgpe-d16/cmos.layout
View File

@ -41,6 +41,7 @@ entries
456 1 e 1 ECC_memory
457 1 e 1 ECC_redirection
458 4 e 11 hypertransport_speed_limit
477 1 e 1 ieee1394_controller
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers

21
src/mainboard/asus/kgpe-d16/romstage.c
View File

@ -165,10 +165,23 @@ static void set_ddr3_voltage(uint8_t node, uint8_t index) {
static void set_peripheral_control_lines(void) {
uint8_t byte;
uint8_t nvram;
uint8_t enable_ieee1394;
/* Enable PCICLK5 (onboard FireWire device) */
outb(0x41, 0xcd6);
outb(0x02, 0xcd7);
enable_ieee1394 = 1;
if (get_option(&nvram, "ieee1394_controller") == CB_SUCCESS)
enable_ieee1394 = nvram & 0x1;
if (enable_ieee1394) {
/* Enable PCICLK5 (onboard FireWire device) */
outb(0x41, 0xcd6);
outb(0x02, 0xcd7);
} else {
/* Disable PCICLK5 (onboard FireWire device) */
outb(0x41, 0xcd6);
outb(0x00, 0xcd7);
}
/* Enable the RTC AltCentury register */
outb(0x41, 0xcd6);
@ -419,4 +432,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
{
return 0;
}
}