intel/xeon_sp, mb/ocp/deltalake: Rework get_stack_busnos()

- Return the busno based on the stack number.
- Replace pci_mmio_read_config32 with pci_io_read_config32 to get the
  register value before mapping the MMIOCFG space.
- Remove the plural `s` as the function now provides one bus number.

Change-Id: I6e78e31b8ab89b1bdcfdeffae2e193e698385186
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/ocp/deltalake/ramstage.c

@@ -213,7 +213,7 @@ static int create_smbios_type9(int *handle, unsigned long *current)
 	uint8_t characteristics_1 = 0;
 	uint8_t characteristics_2 = 0;
 	uint32_t vendor_device_id;
-	uint32_t stack_busnos[6];
+	uint8_t stack_busnos[MAX_IIO_STACK];
 	pci_devfn_t pci_dev;
 	unsigned int cap;
 	uint16_t sltcap;
@@ -221,7 +221,8 @@ static int create_smbios_type9(int *handle, unsigned long *current)
 	if (ipmi_get_pcie_config(&pcie_config) != CB_SUCCESS)
 		printk(BIOS_ERR, "Failed to get IPMI PCIe config\n");
 
-	get_stack_busnos(stack_busnos);
+	for (index = 0; index < ARRAY_SIZE(stack_busnos); index++)
+		stack_busnos[index] = get_stack_busno(index);
 
 	for (index = 0; index < ARRAY_SIZE(slotinfo); index++) {
 		if (pcie_config == PCIE_CONFIG_A) {

src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h

@@ -53,6 +53,7 @@
 #define UBOX_DECS_DEV			8
 #define UBOX_DECS_FUNC			2
 #define UBOX_DECS_CPUBUSNO_CSR		0xcc
+#define UBOX_DECS_CPUBUSNO1_CSR		0xd0
 
 #define VTD_TOLM_CSR			0xd0
 #define VTD_TSEG_BASE_CSR		0xa8

src/soc/intel/xeon_sp/include/soc/util.h

@@ -8,7 +8,7 @@
 
 void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3);
 void unlock_pam_regions(void);
-void get_stack_busnos(uint32_t *bus);
+uint8_t get_stack_busno(const uint8_t stack);
 msr_t read_msr_ppin(void);
 int get_threads_per_package(void);
 int get_platform_thread_count(void);

src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h

@@ -77,6 +77,7 @@
 #define UBOX_DECS_DEV			8
 #define UBOX_DECS_FUNC			2
 #define UBOX_DECS_CPUBUSNO_CSR		0xcc
+#define UBOX_DECS_CPUBUSNO1_CSR		0xd0
 
 #define VTD_TOLM_CSR			0xd0
 #define VTD_TSEG_BASE_CSR		0xa8

src/soc/intel/xeon_sp/util.c

@@ -13,19 +13,15 @@
 #include <soc/util.h>
 #include <timer.h>
 
-void get_stack_busnos(uint32_t *bus)
+uint8_t get_stack_busno(const uint8_t stack)
 {
-	uint32_t reg1, reg2;
-
-	reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC),
-		0xcc);
-	reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC),
-		0xd0);
-
-	for (int i = 0; i < 4; ++i)
-		bus[i] = ((reg1 >> (i * 8)) & 0xff);
-	for (int i = 0; i < 2; ++i)
-		bus[4+i] = ((reg2 >> (i * 8)) & 0xff);
+	if (stack >= MAX_IIO_STACK) {
+		printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack);
+		return 0;
+	}
+	const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC);
+	const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR;
+	return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff;
 }
 
 void unlock_pam_regions(void)