diff --git a/src/mainboard/amd/gardenia/acpi/gpe.asl b/src/mainboard/amd/gardenia/acpi/gpe.asl
index a4aed9a7d9..7756729d3b 100644
--- a/src/mainboard/amd/gardenia/acpi/gpe.asl
+++ b/src/mainboard/amd/gardenia/acpi/gpe.asl
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
+External (\_SB.PCI0.AZHD, DeviceObj)
+
 Scope(\_GPE) {	/* Start Scope GPE */
 
 	/*  General event 3  */
diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl
index 3fd653ed40..545ba14658 100644
--- a/src/mainboard/amd/padmelon/acpi/gpe.asl
+++ b/src/mainboard/amd/padmelon/acpi/gpe.asl
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
+External (\_SB.PCI0.AZHD, DeviceObj)
+
 Scope(\_GPE) {	/* Start Scope GPE */
 
 	/*  General event 3  */
diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c
index ea42b84216..2028f09335 100644
--- a/src/soc/amd/common/block/hda/hda.c
+++ b/src/soc/amd/common/block/hda/hda.c
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
+#include <arch/acpigen.h>
+#include <amdblocks/hda.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
@@ -19,12 +21,23 @@ static const char *hda_acpi_name(const struct device *dev)
 	return "AZHD";
 }
 
+__weak void hda_soc_ssdt_quirks(const struct device *dev)
+{
+}
+
+static void hda_fill_ssdt(const struct device *dev)
+{
+	acpi_device_write_pci_dev(dev);
+	hda_soc_ssdt_quirks(dev);
+}
+
 static struct device_operations hda_audio_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.ops_pci		= &pci_dev_ops_pci,
 	.acpi_name		= hda_acpi_name,
+	.acpi_fill_ssdt		= hda_fill_ssdt,
 };
 
 static const struct pci_driver hdaaudio_driver __pci_driver = {
diff --git a/src/soc/amd/common/block/include/amdblocks/hda.h b/src/soc/amd/common/block/include/amdblocks/hda.h
new file mode 100644
index 0000000000..b59a7b0e02
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/hda.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#ifndef __AMDBLOCKS_HDA_H__
+#define __AMDBLOCKS_HDA_H__
+
+#include <device/device.h>
+
+/* SoC callback to add any quirks to HDA device node in SSDT. */
+void hda_soc_ssdt_quirks(const struct device *dev);
+
+#endif /* __AMDBLOCKS_HDA_H__ */
diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl
index 386556c9d0..67ae6f2bbe 100644
--- a/src/soc/amd/picasso/acpi/northbridge.asl
+++ b/src/soc/amd/picasso/acpi/northbridge.asl
@@ -76,7 +76,3 @@ Device(PBR8) {
 		Return (PS8)			/* PIC Mode */
 	} /* end _PRT */
 } /* end PBR8 */
-
-Device(AZHD) {	/* 0:9.2 - HD Audio */
-	Name(_ADR, 0x00090002)
-} /* end AZHD */
diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl
index c8076015bb..91e43aa5d6 100644
--- a/src/soc/amd/stoneyridge/acpi/northbridge.asl
+++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl
@@ -81,40 +81,3 @@ Device(PBR8) {
 		Return (PS8)			/* PIC Mode */
 	} /* end _PRT */
 } /* end PBR8 */
-
-Device(AZHD) {	/* 0:9.2 - HD Audio */
-	Name(_ADR, 0x00090002)
-	OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
-		Field(AZPD, AnyAcc, NoLock, Preserve) {
-		offset (0x42),
-		NSDI, 1,
-		NSDO, 1,
-		NSEN, 1,
-		offset (0x44),
-		IPCR, 4,
-		offset (0x54),
-		PWST, 2,
-		, 6,
-		PMEB, 1,
-		, 6,
-		PMST, 1,
-		offset (0x62),
-		MMCR, 1,
-		offset (0x64),
-		MMLA, 32,
-		offset (0x68),
-		MMHA, 32,
-		offset (0x6c),
-		MMDT, 16,
-	}
-
-	Method (_INI, 0, NotSerialized)
-	{
-		If (LEqual (OSVR, 0x03))
-		{
-			Store (Zero, NSEN)
-			Store (One, NSDO)
-			Store (One, NSDI)
-		}
-	}
-} /* end AZHD */
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index db715091cf..2aa16b6853 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
+#include <assert.h>
 #include <amdblocks/biosram.h>
+#include <amdblocks/hda.h>
 #include <device/pci_ops.h>
 #include <arch/ioapic.h>
 #include <arch/acpi.h>
@@ -501,3 +503,55 @@ void SetNbMidParams(GNB_MID_CONFIGURATION *params)
 	params->iGpuVgaMode = 0;
 	params->GnbIoapicAddress = IO_APIC2_ADDR;
 }
+
+void hda_soc_ssdt_quirks(const struct device *dev)
+{
+	const char *scope = acpi_device_path(dev);
+	static const struct fieldlist list[] = {
+		FIELDLIST_OFFSET(0x42),
+		FIELDLIST_NAMESTR("NSDI", 1),
+		FIELDLIST_NAMESTR("NSDO", 1),
+		FIELDLIST_NAMESTR("NSEN", 1),
+	};
+	struct opregion opreg = OPREGION("AZPD", PCI_CONFIG, 0x0, 0x100);
+
+	assert(scope);
+
+	acpigen_write_scope(scope);
+
+	/*
+	 * OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+	 * Field (AZPD, AnyAcc, NoLock, Preserve) {
+	 *	Offset (0x42),
+	 *	NSDI, 1,
+	 *	NSDO, 1,
+	 *	NSEN, 1,
+	 * }
+	 */
+	acpigen_write_opregion(&opreg);
+	acpigen_write_field(opreg.name, list, ARRAY_SIZE(list),
+			    FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE);
+
+	/*
+	 * Method (_INI, 0, NotSerialized) {
+	 *	If (LEqual (OSVR, 0x03)) {
+	 *		Store (Zero, NSEN)
+	 *		Store (One, NSDO)
+	 *		Store (One, NSDI)
+	 *	}
+	 * }
+	 */
+	acpigen_write_method("_INI", 0);
+
+	acpigen_write_if_lequal_namestr_int("OSVR", 0x03);
+
+	acpigen_write_store_op_to_namestr(ONE_OP, "NSEN");
+	acpigen_write_store_op_to_namestr(ZERO_OP, "NSDO");
+	acpigen_write_store_op_to_namestr(ZERO_OP, "NSDI");
+
+	acpigen_pop_len(); /* If */
+
+	acpigen_pop_len(); /* Method _INI */
+
+	acpigen_pop_len(); /* Scope */
+}