fsp_broadwell_de: Correct access to SIRQ_CNTL register

The serial IRQ configuration register is only 8 bit wide so switch the
PCI access from 16 bits to 8 bits.

Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16534
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/intel/fsp_broadwell_de/southcluster.c

@@ -215,7 +215,7 @@ static void sc_init(struct device *dev)
 		PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
 
 	/* Program Serial IRQ register. */
-	pci_write_config16(dev, 0x64, 0xd0);
+	pci_write_config8(dev, 0x64, 0xd0);
 
 	sc_pirq_init(dev);
 	write_pci_config_irqs();