From 91b2024bae0b35967b07eb30084c3f55fe5aaa4b Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Tue, 23 Feb 2021 14:03:43 +0530 Subject: [PATCH] soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining We need to modify update CmdMirror and LpDdrDqDqsRetraining parameters for ADLRVP board. Allowing this parameters to be filled by devicetree will allow flexibility to update values as per board designs. Note that both UPDs are applicable for both DDR and Lpddr memory types. BUG=None BRANCH=None TEST=Build works and UPD values have been filled correctly Change-Id: I55b4b4aee46231c8c38e208c357b4376ecf6e9d9 Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/51027 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/include/soc/meminit.h | 6 ++++++ src/soc/intel/alderlake/meminit.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 96e049cf99..49e3c769bc 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -103,6 +103,12 @@ struct mb_cfg { /* Board type */ uint8_t UserBd; + + /* Command Mirror */ + uint8_t CmdMirror; + + /* Enable/Disable TxDqDqs Retraining for Lp4/Lp5/DDR */ + uint8_t LpDdrDqDqsReTraining; }; void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 48d338600d..33f26da87f 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -226,6 +226,12 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, mem_cfg->UserBd = mb_cfg->UserBd; set_rcomp_config(mem_cfg, mb_cfg); + /* Fill command mirror for memory */ + mem_cfg->CmdMirror = mb_cfg->CmdMirror; + + /* Fill LpDdrrDqDqs Retraining for memory */ + mem_cfg->LpDdrDqDqsReTraining = mb_cfg->LpDdrDqDqsReTraining; + switch (mb_cfg->type) { case MEM_TYPE_DDR4: case MEM_TYPE_DDR5: