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intel/quark: Use common romstage entry 

Change-Id: Ifb2adcdef7265d43cb2bf6886f126f1a17bf08a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2019-08-18 05:07:47 +03:00
parent e0c084cab3
commit 91bc620702
2 changed files with 2 additions and 7 deletions
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1
src/soc/intel/quark/romstage/Makefile.inc
View File

@ -22,5 +22,6 @@ romstage-y += mtrr.c
romstage-y += pcie.c romstage-y += pcie.c
romstage-y += report_platform.c romstage-y += report_platform.c
romstage-y += romstage.c romstage-y += romstage.c
romstage-y += ../../../../cpu/intel/car/romstage.c
postcar-y += mtrr.c postcar-y += mtrr.c

8
src/soc/intel/quark/romstage/fsp2_0.c
View File

@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <arch/cpu.h>
#include <arch/romstage.h> #include <arch/romstage.h>
#include <arch/symbols.h> #include <arch/symbols.h>
#include <console/console.h> #include <console/console.h>
@ -28,9 +27,7 @@
#include <soc/reg_access.h> #include <soc/reg_access.h>
#include <soc/storage_test.h> #include <soc/storage_test.h>
static struct postcar_frame early_mtrrs; void mainboard_romstage_entry(void)
asmlinkage void car_stage_entry(void)
{ {
bool s3wake; bool s3wake;
@ -61,9 +58,6 @@ asmlinkage void car_stage_entry(void)
/* Initialize the PCIe bridges */ /* Initialize the PCIe bridges */
pcie_init(); pcie_init();
prepare_and_run_postcar(&early_mtrrs);
/* We do not return here. */
} }
static struct chipset_power_state power_state; static struct chipset_power_state power_state;