PCIEXP_PLUGIN_SUPPORT: Change dependency on PCI access
Some PCI-e capability registers are located starting from 0x100, these are not accessible using the conventional PCI IO config operations at 0xcf8/0xcfc, unless PCI_CFG_EXT_IO was selected. Thus any feature that calls pciexp_find_extended_cap() depends on either MMCONF_SUPPORT_DEFAULT or PCI_CFG_EXT_IO being enabled on the platform. In theory there can be system without MMCONF_SUPPORT, but with complete PCI Express configuration space available using PCI_CFG_EXT_IO. Do not use explicit PCI MMCONF operations here, but rely on the default PCI access method to be able to access all of the configuration space. While at it, convert to IS_ENABLED() everywhere in the source and organize Kconfig file better. Change-Id: Ica6e16d2fb2adc532e644c4b2c47806490235715 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17546 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
parent
df96a702ba
commit
91bfa8e7ea
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@ -227,11 +227,6 @@ config PCIX_PLUGIN_SUPPORT
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depends on PCI
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default y
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config PCIEXP_PLUGIN_SUPPORT
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bool
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depends on PCI
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default y
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config CARDBUS_PLUGIN_SUPPORT
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bool
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depends on PCI
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@ -242,10 +237,16 @@ config AZALIA_PLUGIN_SUPPORT
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depends on PCI
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default n
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config PCIEXP_PLUGIN_SUPPORT
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bool
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depends on PCI
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default y
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if PCIEXP_PLUGIN_SUPPORT
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config PCIEXP_COMMON_CLOCK
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prompt "Enable PCIe Common Clock"
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bool
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depends on PCIEXP_PLUGIN_SUPPORT
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default n
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help
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Detect and enable Common Clock on PCIe links.
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@ -253,7 +254,6 @@ config PCIEXP_COMMON_CLOCK
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config PCIEXP_ASPM
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prompt "Enable PCIe ASPM"
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bool
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depends on PCIEXP_PLUGIN_SUPPORT
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default n
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help
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Detect and enable ASPM on PCIe links.
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@ -261,11 +261,20 @@ config PCIEXP_ASPM
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config PCIEXP_CLK_PM
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prompt "Enable PCIe Clock Power Management"
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bool
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depends on PCIEXP_PLUGIN_SUPPORT
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default n
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help
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Detect and enable Clock Power Management on PCIe.
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config PCIEXP_L1_SUB_STATE
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prompt "Enable PCIe ASPM L1 SubState"
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bool
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depends on (MMCONF_SUPPORT_DEFAULT || PCI_IO_CFG_EXT)
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default n
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help
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Detect and enable ASPM on PCIe links.
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endif # PCIEXP_PLUGIN_SUPPORT
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config EARLY_PCI_BRIDGE
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bool "Early PCI bridge"
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depends on PCI
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@ -278,14 +287,6 @@ config EARLY_PCI_BRIDGE
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This option enables static configuration for a single pre-defined
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PCI bridge function on bus 0.
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config PCIEXP_L1_SUB_STATE
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prompt "Enable PCIe ASPM L1 SubState"
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bool
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depends on PCIEXP_PLUGIN_SUPPORT && MMCONF_SUPPORT
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default n
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help
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Detect and enable ASPM on PCIe links.
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if EARLY_PCI_BRIDGE
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config EARLY_PCI_BRIDGE_DEVICE
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@ -21,7 +21,6 @@
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#include <device/pci_ids.h>
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#include <device/pciexp.h>
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#if IS_ENABLED(CONFIG_MMCONF_SUPPORT)
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unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap)
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{
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unsigned int this_cap_offset, next_cap_offset;
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@ -29,10 +28,10 @@ unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap)
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this_cap_offset = PCIE_EXT_CAP_OFFSET;
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do {
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this_cap = pci_mmio_read_config32(dev, this_cap_offset);
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this_cap = pci_read_config32(dev, this_cap_offset);
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next_cap_offset = this_cap >> 20;
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this_cap &= 0xffff;
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cafe = pci_mmio_read_config32(dev, this_cap_offset + 4);
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cafe = pci_read_config32(dev, this_cap_offset + 4);
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cafe &= 0xffff;
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if (this_cap == cap)
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return this_cap_offset;
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@ -44,9 +43,7 @@ unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap)
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return 0;
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}
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#endif
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#if CONFIG_PCIEXP_COMMON_CLOCK
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/*
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* Re-train a PCIe link
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*/
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@ -109,9 +106,7 @@ static void pciexp_enable_common_clock(device_t root, unsigned root_cap,
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pciexp_retrain_link(root, root_cap);
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}
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}
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#endif /* CONFIG_PCIEXP_COMMON_CLOCK */
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#if CONFIG_PCIEXP_CLK_PM
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static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap)
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{
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/* check if per port clk req is supported in device */
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@ -126,17 +121,15 @@ static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap)
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lnkctl = lnkctl | PCI_EXP_EN_CLK_PM;
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pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
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}
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#endif /* CONFIG_PCIEXP_CLK_PM */
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#if IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE) && IS_ENABLED(CONFIG_MMCONF_SUPPORT)
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static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
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{
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u32 reg32;
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reg32 = pci_mmio_read_config32(dev, reg);
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reg32 = pci_read_config32(dev, reg);
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reg32 &= mask;
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reg32 |= or;
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pci_mmio_write_config32(dev, reg, reg32);
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pci_write_config32(dev, reg, reg32);
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}
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static void pciexp_config_max_latency(device_t root, device_t dev)
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@ -170,7 +163,7 @@ static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap,
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unsigned int power_on_scale = (*data >> 16) & 0x3;
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unsigned int power_on_value = (*data >> 19) & 0x1f;
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unsigned int endp_data = pci_mmio_read_config32(dev, endp_cap + 4);
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unsigned int endp_data = pci_read_config32(dev, endp_cap + 4);
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unsigned int endp_L1SubStateSupport = endp_data & 0xf;
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unsigned int endp_comm_mode_restore_time = (endp_data >> 8) & 0xff;
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unsigned int endp_power_on_scale = (endp_data >> 16) & 0x3;
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@ -200,7 +193,7 @@ static void pciexp_L1_substate_commit(device_t root, device_t dev,
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{
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device_t dev_t;
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unsigned char L1_ss_ok;
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unsigned int rp_L1_support = pci_mmio_read_config32(root, root_cap + 4);
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unsigned int rp_L1_support = pci_read_config32(root, root_cap + 4);
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unsigned int L1SubStateSupport;
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unsigned int comm_mode_rst_time;
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unsigned int power_on_scale;
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@ -282,9 +275,7 @@ static void pciexp_config_L1_sub_state(device_t root, device_t dev)
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pciexp_L1_substate_commit(root, dev, root_cap, end_cap);
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}
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#endif /* CONFIG_PCIEXP_L1_SUB_STATE */
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#if CONFIG_PCIEXP_ASPM
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/*
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* Determine the ASPM L0s or L1 exit latency for a link
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* by checking both root port and endpoint and returning
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@ -371,7 +362,6 @@ static void pciexp_enable_aspm(device_t root, unsigned root_cap,
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printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]);
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}
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#endif /* CONFIG_PCIEXP_ASPM */
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static void pciexp_tune_dev(device_t dev)
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{
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@ -386,25 +376,21 @@ static void pciexp_tune_dev(device_t dev)
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if (!root_cap)
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return;
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#if CONFIG_PCIEXP_COMMON_CLOCK
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/* Check for and enable Common Clock */
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pciexp_enable_common_clock(root, root_cap, dev, cap);
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#endif
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if (IS_ENABLED(CONFIG_PCIEXP_COMMON_CLOCK))
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pciexp_enable_common_clock(root, root_cap, dev, cap);
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#if CONFIG_PCIEXP_CLK_PM
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/* Check if per port CLK req is supported by endpoint*/
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pciexp_enable_clock_power_pm(dev, cap);
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#endif
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if (IS_ENABLED(CONFIG_PCIEXP_CLK_PM))
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pciexp_enable_clock_power_pm(dev, cap);
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#if CONFIG_PCIEXP_L1_SUB_STATE
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/* Enable L1 Sub-State when both root port and endpoint support */
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pciexp_config_L1_sub_state(root, dev);
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#endif /* CONFIG_PCIEXP_L1_SUB_STATE */
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if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE))
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pciexp_config_L1_sub_state(root, dev);
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#if CONFIG_PCIEXP_ASPM
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/* Check for and enable ASPM */
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pciexp_enable_aspm(root, root_cap, dev, cap);
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#endif
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if (IS_ENABLED(CONFIG_PCIEXP_ASPM))
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pciexp_enable_aspm(root, root_cap, dev, cap);
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}
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void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
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