PCIEXP_PLUGIN_SUPPORT: Change dependency on PCI access

Some PCI-e capability registers are located starting from
0x100, these are not accessible using the conventional
PCI IO config operations at 0xcf8/0xcfc, unless PCI_CFG_EXT_IO
was selected.

Thus any feature that calls pciexp_find_extended_cap()
depends on either MMCONF_SUPPORT_DEFAULT or PCI_CFG_EXT_IO
being enabled on the platform.

In theory there can be system without MMCONF_SUPPORT, but
with complete PCI Express configuration space available
using PCI_CFG_EXT_IO. Do not use explicit PCI MMCONF
operations here, but rely on the default PCI access
method to be able to access all of the configuration space.

While at it, convert to IS_ENABLED() everywhere in the source
and organize Kconfig file better.

Change-Id: Ica6e16d2fb2adc532e644c4b2c47806490235715
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17546
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/device/Kconfig

@@ -227,11 +227,6 @@ config PCIX_PLUGIN_SUPPORT
 	depends on PCI
 	default y
 
-config PCIEXP_PLUGIN_SUPPORT
-	bool
-	depends on PCI
-	default y
-
 config CARDBUS_PLUGIN_SUPPORT
 	bool
 	depends on PCI
@@ -242,10 +237,16 @@ config AZALIA_PLUGIN_SUPPORT
 	depends on PCI
 	default n
 
+config PCIEXP_PLUGIN_SUPPORT
+	bool
+	depends on PCI
+	default y
+
+if PCIEXP_PLUGIN_SUPPORT
+
 config PCIEXP_COMMON_CLOCK
 	prompt "Enable PCIe Common Clock"
 	bool
-	depends on PCIEXP_PLUGIN_SUPPORT
 	default n
 	help
 	  Detect and enable Common Clock on PCIe links.
@@ -253,7 +254,6 @@ config PCIEXP_COMMON_CLOCK
 config PCIEXP_ASPM
 	prompt "Enable PCIe ASPM"
 	bool
-	depends on PCIEXP_PLUGIN_SUPPORT
 	default n
 	help
 	  Detect and enable ASPM on PCIe links.
@@ -261,11 +261,20 @@ config PCIEXP_ASPM
 config PCIEXP_CLK_PM
 	prompt "Enable PCIe Clock Power Management"
 	bool
-	depends on PCIEXP_PLUGIN_SUPPORT
 	default n
 	help
 	  Detect and enable Clock Power Management on PCIe.
 
+config PCIEXP_L1_SUB_STATE
+	prompt "Enable PCIe ASPM L1 SubState"
+	bool
+	depends on (MMCONF_SUPPORT_DEFAULT || PCI_IO_CFG_EXT)
+	default n
+	help
+	  Detect and enable ASPM on PCIe links.
+
+endif # PCIEXP_PLUGIN_SUPPORT
+
 config EARLY_PCI_BRIDGE
 	bool "Early PCI bridge"
 	depends on PCI
@@ -278,14 +287,6 @@ config EARLY_PCI_BRIDGE
 	  This option enables static configuration for a single pre-defined
 	  PCI bridge function on bus 0.
 
-config PCIEXP_L1_SUB_STATE
-	prompt "Enable PCIe ASPM L1 SubState"
-	bool
-	depends on PCIEXP_PLUGIN_SUPPORT && MMCONF_SUPPORT
-	default n
-	help
-	  Detect and enable ASPM on PCIe links.
-
 if EARLY_PCI_BRIDGE
 
 config EARLY_PCI_BRIDGE_DEVICE

src/device/pciexp_device.c

@@ -21,7 +21,6 @@
 #include <device/pci_ids.h>
 #include <device/pciexp.h>
 
-#if IS_ENABLED(CONFIG_MMCONF_SUPPORT)
 unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap)
 {
 	unsigned int this_cap_offset, next_cap_offset;
@@ -29,10 +28,10 @@ unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap)
 
 	this_cap_offset = PCIE_EXT_CAP_OFFSET;
 	do {
-		this_cap = pci_mmio_read_config32(dev, this_cap_offset);
+		this_cap = pci_read_config32(dev, this_cap_offset);
 		next_cap_offset = this_cap >> 20;
 		this_cap &= 0xffff;
-		cafe = pci_mmio_read_config32(dev, this_cap_offset + 4);
+		cafe = pci_read_config32(dev, this_cap_offset + 4);
 		cafe &= 0xffff;
 		if (this_cap == cap)
 			return this_cap_offset;
@@ -44,9 +43,7 @@ unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap)
 
 	return 0;
 }
-#endif
 
-#if CONFIG_PCIEXP_COMMON_CLOCK
 /*
  * Re-train a PCIe link
  */
@@ -109,9 +106,7 @@ static void pciexp_enable_common_clock(device_t root, unsigned root_cap,
 		pciexp_retrain_link(root, root_cap);
 	}
 }
-#endif /* CONFIG_PCIEXP_COMMON_CLOCK */
 
-#if CONFIG_PCIEXP_CLK_PM
 static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap)
 {
 	/* check if per port clk req is supported in device */
@@ -126,17 +121,15 @@ static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap)
 	lnkctl = lnkctl | PCI_EXP_EN_CLK_PM;
 	pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
 }
-#endif /* CONFIG_PCIEXP_CLK_PM */
 
-#if IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE) && IS_ENABLED(CONFIG_MMCONF_SUPPORT)
 static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
 {
 	u32 reg32;
 
-	reg32 = pci_mmio_read_config32(dev, reg);
+	reg32 = pci_read_config32(dev, reg);
 	reg32 &= mask;
 	reg32 |= or;
-	pci_mmio_write_config32(dev, reg, reg32);
+	pci_write_config32(dev, reg, reg32);
 }
 
 static void pciexp_config_max_latency(device_t root, device_t dev)
@@ -170,7 +163,7 @@ static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap,
 	unsigned int power_on_scale = (*data >> 16) & 0x3;
 	unsigned int power_on_value = (*data >> 19) & 0x1f;
 
-	unsigned int endp_data = pci_mmio_read_config32(dev, endp_cap + 4);
+	unsigned int endp_data = pci_read_config32(dev, endp_cap + 4);
 	unsigned int endp_L1SubStateSupport = endp_data & 0xf;
 	unsigned int endp_comm_mode_restore_time = (endp_data >> 8) & 0xff;
 	unsigned int endp_power_on_scale = (endp_data >> 16) & 0x3;
@@ -200,7 +193,7 @@ static void pciexp_L1_substate_commit(device_t root, device_t dev,
 {
 	device_t dev_t;
 	unsigned char L1_ss_ok;
-	unsigned int rp_L1_support = pci_mmio_read_config32(root, root_cap + 4);
+	unsigned int rp_L1_support = pci_read_config32(root, root_cap + 4);
 	unsigned int L1SubStateSupport;
 	unsigned int comm_mode_rst_time;
 	unsigned int power_on_scale;
@@ -282,9 +275,7 @@ static void pciexp_config_L1_sub_state(device_t root, device_t dev)
 
 	pciexp_L1_substate_commit(root, dev, root_cap, end_cap);
 }
-#endif /* CONFIG_PCIEXP_L1_SUB_STATE */
 
-#if CONFIG_PCIEXP_ASPM
 /*
  * Determine the ASPM L0s or L1 exit latency for a link
  * by checking both root port and endpoint and returning
@@ -371,7 +362,6 @@ static void pciexp_enable_aspm(device_t root, unsigned root_cap,
 
 	printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]);
 }
-#endif /* CONFIG_PCIEXP_ASPM */
 
 static void pciexp_tune_dev(device_t dev)
 {
@@ -386,25 +376,21 @@ static void pciexp_tune_dev(device_t dev)
 	if (!root_cap)
 		return;
 
-#if CONFIG_PCIEXP_COMMON_CLOCK
 	/* Check for and enable Common Clock */
-	pciexp_enable_common_clock(root, root_cap, dev, cap);
+	if (IS_ENABLED(CONFIG_PCIEXP_COMMON_CLOCK))
-#endif
+		pciexp_enable_common_clock(root, root_cap, dev, cap);
 
-#if CONFIG_PCIEXP_CLK_PM
 	/* Check if per port CLK req is supported by endpoint*/
-	pciexp_enable_clock_power_pm(dev, cap);
+	if (IS_ENABLED(CONFIG_PCIEXP_CLK_PM))
-#endif
+		pciexp_enable_clock_power_pm(dev, cap);
 
-#if CONFIG_PCIEXP_L1_SUB_STATE
 	/* Enable L1 Sub-State when both root port and endpoint support */
-	pciexp_config_L1_sub_state(root, dev);
+	if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE))
-#endif /* CONFIG_PCIEXP_L1_SUB_STATE */
+		pciexp_config_L1_sub_state(root, dev);
 
-#if CONFIG_PCIEXP_ASPM
 	/* Check for and enable ASPM */
-	pciexp_enable_aspm(root, root_cap, dev, cap);
+	if (IS_ENABLED(CONFIG_PCIEXP_ASPM))
-#endif
+		pciexp_enable_aspm(root, root_cap, dev, cap);
 }
 
 void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,