ChromeOS: Fix <vc/google/chromeos/chromeos.h>

Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/drivers/intel/fsp1_1/romstage.c

@@ -18,7 +18,6 @@
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 static void raminit_common(struct romstage_params *params)
 {

src/ec/google/chromeec/vboot_storage.c

@@ -3,7 +3,7 @@
 #include <assert.h>
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
-#include <vendorcode/google/chromeos/chromeos.h>
+#include <security/vboot/vboot_common.h>
 
 #define VBOOT_HASH_VSLOT 0
 #define VBOOT_HASH_VSLOT_MASK (1 << (VBOOT_HASH_VSLOT))

src/mainboard/google/auron/ec.c

@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
 #include "ec.h"

src/mainboard/google/brya/variants/anahera/gpio.c

@@ -4,7 +4,6 @@
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
 #include <soc/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage */
 static const struct pad_config override_gpio_table[] = {

src/mainboard/google/brya/variants/brask/gpio.c

@@ -4,7 +4,6 @@
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
 #include <soc/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {

src/mainboard/google/brya/variants/felwinter/gpio.c

@@ -4,7 +4,6 @@
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
 #include <soc/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage */
 static const struct pad_config override_gpio_table[] = {

src/mainboard/google/brya/variants/gimble/gpio.c

@@ -4,7 +4,6 @@
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
 #include <soc/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage */
 static const struct pad_config override_gpio_table[] = {

src/mainboard/google/brya/variants/kano/gpio.c

@@ -4,7 +4,6 @@
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
 #include <soc/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage */
 static const struct pad_config override_gpio_table[] = {

src/mainboard/google/brya/variants/primus/gpio.c

@@ -4,7 +4,6 @@
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
 #include <soc/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage */
 static const struct pad_config override_gpio_table[] = {

src/mainboard/google/brya/variants/redrix/gpio.c

@@ -4,7 +4,6 @@
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
 #include <soc/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage */
 static const struct pad_config override_gpio_table[] = {

src/mainboard/google/brya/variants/taeko/gpio.c

@@ -4,7 +4,6 @@
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
 #include <soc/gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage */
 static const struct pad_config override_gpio_table[] = {

src/mainboard/google/cyan/ec.c

@@ -4,7 +4,6 @@
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
 #include "ec.h"
-#include <vendorcode/google/chromeos/chromeos.h>
 
 void mainboard_ec_init(void)
 {

src/mainboard/google/dedede/variants/blipper/gpio.c

@@ -3,7 +3,6 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {

src/mainboard/google/dedede/variants/boten/gpio.c

@@ -3,7 +3,6 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {

src/mainboard/google/dedede/variants/gooey/gpio.c

@@ -3,7 +3,6 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {

src/mainboard/google/dedede/variants/metaknight/gpio.c

@@ -3,7 +3,6 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {

src/mainboard/google/deltaur/variants/baseboard/gpio.c

@@ -5,6 +5,7 @@
 #include <baseboard/gpio.h>
 #include <soc/gpio.h>
 #include <variant/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 static const struct pad_config gpio_table[] = {
 	/* A0 thru A6 are ESPI, configured elsewhere */

src/mainboard/google/fizz/variants/baseboard/gpio.c

@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage */
 /* Leave eSPI pins untouched from default settings */

src/mainboard/google/foster/mainboard.c

@@ -12,7 +12,6 @@
 #include <soc/nvidia/tegra/dc.h>
 #include <soc/display.h>
 
-#include <vendorcode/google/chromeos/chromeos.h>
 
 static const struct pad_config sdmmc1_pad[] = {
 	/* MMC1(SDCARD) */

src/mainboard/google/gru/mainboard.c

@@ -3,6 +3,7 @@
 #include <assert.h>
 #include <bl31.h>
 #include <boardid.h>
+#include <bootmode.h>
 #include <console/console.h>
 #include <device/mmio.h>
 #include <delay.h>
@@ -17,7 +18,6 @@
 #include <soc/i2c.h>
 #include <soc/usb.h>
 #include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "board.h"
 

src/mainboard/google/hatch/variants/baseboard/gpio.c

@@ -4,6 +4,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 static const struct pad_config gpio_table[] = {
 	/* A0  : GPP_A0 ==> NC */

src/mainboard/google/nyan/mainboard.c

@@ -13,7 +13,6 @@
 #include <soc/pmc.h>
 #include <soc/spi.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
 

src/mainboard/google/nyan_big/mainboard.c

@@ -13,7 +13,6 @@
 #include <soc/spi.h>
 #include <soc/nvidia/tegra/usb.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
 

src/mainboard/google/nyan_blaze/mainboard.c

@@ -13,7 +13,6 @@
 #include <soc/pmc.h>
 #include <soc/spi.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
 

src/mainboard/google/oak/mainboard.c

@@ -17,7 +17,6 @@
 #include <soc/mtcmos.h>
 #include <soc/pll.h>
 #include <soc/usb.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <framebuffer_info.h>
 
 enum {

src/mainboard/google/octopus/variants/baseboard/gpio.c

@@ -4,6 +4,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /*
  * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'

src/mainboard/google/poppy/variants/baseboard/gpio.c

@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage */
 /* Leave eSPI pins untouched from default settings */

src/mainboard/google/reef/variants/baseboard/gpio.c

@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /*
  * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'

src/mainboard/google/reef/variants/coral/gpio.c

@@ -4,6 +4,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /*
  * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'

src/mainboard/google/veyron/mainboard.c

@@ -16,7 +16,6 @@
 #include <soc/spi.h>
 #include <soc/i2c.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "board.h"
 

src/mainboard/google/veyron/romstage.c

@@ -17,7 +17,6 @@
 #include <symbols.h>
 #include <timestamp.h>
 #include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "board.h"
 

src/mainboard/google/veyron_mickey/mainboard.c

@@ -15,7 +15,6 @@
 #include <soc/spi.h>
 #include <soc/i2c.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "board.h"
 

src/mainboard/google/veyron_mickey/romstage.c

@@ -17,7 +17,6 @@
 #include <symbols.h>
 #include <timestamp.h>
 #include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "board.h"
 

src/mainboard/google/veyron_rialto/mainboard.c

@@ -16,7 +16,6 @@
 #include <soc/spi.h>
 #include <soc/i2c.h>
 #include <symbols.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <security/vboot/vboot_common.h>
 
 #include "board.h"

src/mainboard/google/veyron_rialto/romstage.c

@@ -17,7 +17,6 @@
 #include <symbols.h>
 #include <timestamp.h>
 #include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "board.h"
 

src/mainboard/google/volteer/variants/baseboard/gpio.c

@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage */
 /* Leave eSPI pins untouched from default settings */

src/mainboard/intel/adlrvp/gpio.c

@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {

src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c

@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
 static const struct pad_config gpio_table[] = {

src/mainboard/intel/glkrvp/variants/baseboard/gpio.c

@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /*
  * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'

src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c

@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {

src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c

@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {

src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c

@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {

src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c

@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage */
 /* Leave eSPI pins untouched from default settings */

src/mainboard/intel/strago/ec.c

@@ -4,7 +4,6 @@
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
 #include "ec.h"
-#include <vendorcode/google/chromeos/chromeos.h>
 
 void mainboard_ec_init(void)
 {

src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c

@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {

src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c

@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage*/
 static const struct pad_config gpio_table[] = {

src/soc/intel/cannonlake/romstage/fsp_params.c

@@ -13,7 +13,6 @@
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "../chip.h"
 

src/vendorcode/google/chromeos/chromeos.h

@@ -5,11 +5,6 @@
 
 #include <stddef.h>
 #include <stdint.h>
-#include <bootmode.h>
-#include <device/device.h>
-#include <rules.h>
-#include <security/vboot/misc.h>
-#include <security/vboot/vboot_common.h>
 #include <types.h>
 
 #if CONFIG(CHROMEOS)

src/vendorcode/google/chromeos/cr50_enable_update.c

@@ -7,6 +7,7 @@
 #include <halt.h>
 #include <security/tpm/tss.h>
 #include <vb2_api.h>
+#include <security/vboot/misc.h>
 #include <security/vboot/vboot_common.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <timestamp.h>

src/vendorcode/google/chromeos/vpd_calibration.c

@@ -3,6 +3,7 @@
 #include <b64_decode.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include <stdlib.h>
 #include <string.h>
 
 #include <vendorcode/google/chromeos/chromeos.h>