first cut
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson
parent
2906362ea7
commit
91d60a8fca
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@ -1,3 +1,11 @@
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#
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# Config file for IBM CPC710
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#
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initobject cpc710.o
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initobject cpc710_pci.o
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initobject cpc710_sdram.o
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object cpc710.o
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object cpc710_pci.o
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object cpc710_sdram.o
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@ -1,254 +1,77 @@
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <stdint.h>
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#include <arch/io.h>
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#include "cpc710.h"
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#define MCCR_DEFAULT \
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CPC710_MCCR_DIAG_MODE | \
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CPC710_MCCR_ECC_DISABLE | \
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CPC710_MCCR_REFRESH_7CY | \
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CPC710_MCCR_DATA_MASK | \
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CPC710_MCCR_FIXED_BITS
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#include "pcippc2.h"
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#include "i2c.h"
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void cpc710_init(void);
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extern void cpc710_pci_init(void);
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typedef struct cpc710_mem_org_s
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void
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setCPC710(uint32_t addr, uint32_t data)
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{
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u8 rows;
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u8 cols;
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u8 banks2;
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u8 org;
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} cpc710_mem_org_t;
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static int cpc710_compute_mcer (u32 * mcer,
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unsigned long *
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size,
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unsigned int sdram);
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static int cpc710_eeprom_checksum (unsigned int sdram);
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static u8 cpc710_eeprom_read (unsigned int sdram,
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unsigned int offset);
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static u32 cpc710_mcer_mem [] =
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{
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0x000003f3, /* 18 lines, 4 Mb */
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0x000003e3, /* 19 lines, 8 Mb */
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0x000003c3, /* 20 lines, 16 Mb */
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0x00000383, /* 21 lines, 32 Mb */
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0x00000303, /* 22 lines, 64 Mb */
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0x00000203, /* 23 lines, 128 Mb */
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0x00000003, /* 24 lines, 256 Mb */
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0x00000002, /* 25 lines, 512 Mb */
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0x00000001 /* 26 lines, 1024 Mb */
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};
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static cpc710_mem_org_t cpc710_mem_org [] =
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{
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{ 0x0c, 0x09, 0x02, 0x00 }, /* 0000: 12/ 9/2 */
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{ 0x0d, 0x09, 0x02, 0x00 }, /* 0000: 13/ 9/2 */
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{ 0x0d, 0x0a, 0x02, 0x00 }, /* 0000: 13/10/2 */
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{ 0x0d, 0x0b, 0x02, 0x00 }, /* 0000: 13/11/2 */
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{ 0x0d, 0x0c, 0x02, 0x00 }, /* 0000: 13/12/2 */
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{ 0x0e, 0x0c, 0x02, 0x00 }, /* 0000: 14/12/2 */
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{ 0x0b, 0x08, 0x02, 0x01 }, /* 0001: 11/ 8/2 */
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{ 0x0b, 0x09, 0x01, 0x02 }, /* 0010: 11/ 9/1 */
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{ 0x0b, 0x0a, 0x01, 0x03 }, /* 0011: 11/10/1 */
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{ 0x0c, 0x08, 0x02, 0x04 }, /* 0100: 12/ 8/2 */
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{ 0x0c, 0x0a, 0x02, 0x05 }, /* 0101: 12/10/2 */
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{ 0x0d, 0x08, 0x01, 0x06 }, /* 0110: 13/ 8/1 */
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{ 0x0d, 0x08, 0x02, 0x07 }, /* 0111: 13/ 8/2 */
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{ 0x0d, 0x09, 0x01, 0x08 }, /* 1000: 13/ 9/1 */
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{ 0x0d, 0x0a, 0x01, 0x09 }, /* 1001: 13/10/1 */
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{ 0x0b, 0x08, 0x01, 0x0a }, /* 1010: 11/ 8/1 */
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{ 0x0c, 0x08, 0x01, 0x0b }, /* 1011: 12/ 8/1 */
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{ 0x0c, 0x09, 0x01, 0x0c }, /* 1100: 12/ 9/1 */
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{ 0x0e, 0x09, 0x02, 0x0d }, /* 1101: 14/ 9/2 */
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{ 0x0e, 0x0a, 0x02, 0x0e }, /* 1110: 14/10/2 */
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{ 0x0e, 0x0b, 0x02, 0x0f } /* 1111: 14/11/2 */
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};
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unsigned long cpc710_ram_init (void)
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{
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unsigned long memsize = 0;
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unsigned long bank_size;
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u32 mcer;
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#ifndef CFG_RAMBOOT
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/* Clear memory banks
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*/
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out32(REG(SDRAM0, MCER0), 0);
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out32(REG(SDRAM0, MCER1), 0);
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out32(REG(SDRAM0, MCER2), 0);
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out32(REG(SDRAM0, MCER3), 0);
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out32(REG(SDRAM0, MCER4), 0);
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out32(REG(SDRAM0, MCER5), 0);
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out32(REG(SDRAM0, MCER6), 0);
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out32(REG(SDRAM0, MCER7), 0);
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iobarrier_rw();
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/* Disable memory
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*/
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out32(REG(SDRAM0,MCCR), 0x13b06000);
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iobarrier_rw();
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#endif
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/* Only the first memory bank is initialised now
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*/
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if (! cpc710_compute_mcer(& mcer, & bank_size, 0))
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{
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puts("Unsupported SDRAM type !\n");
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hang();
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}
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memsize += bank_size;
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#ifndef CFG_RAMBOOT
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/* Enable bank, zero start
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*/
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out32(REG(SDRAM0, MCER0), mcer | 0x80000000);
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iobarrier_rw();
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#endif
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#ifndef CFG_RAMBOOT
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/* Enable memory
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*/
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out32(REG(SDRAM0, MCCR), in32(REG(SDRAM0, MCCR)) | 0x80000000);
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/* Wait until initialisation finished
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*/
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while (! (in32 (REG(SDRAM0, MCCR)) & 0x20000000))
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{
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iobarrier_rw();
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}
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/* Clear Memory Error Status and Address registers
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*/
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out32(REG(SDRAM0, MESR), 0);
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out32(REG(SDRAM0, MEAR), 0);
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iobarrier_rw();
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/* ECC is not configured now
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*/
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#endif
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/* Memory size counter
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*/
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out32(REG(CPC0, RGBAN1), memsize);
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return memsize;
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out_be32((unsigned *)(CPC710_SCA_CPC0 + addr), data);
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}
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static int cpc710_compute_mcer (
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u32 * mcer,
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unsigned long * size,
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unsigned int sdram)
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uint32_t
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getCPC710(uint32_t addr)
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{
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u8 rows;
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u8 cols;
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u8 banks2;
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unsigned int lines;
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u32 mc = 0;
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unsigned int i;
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cpc710_mem_org_t * org = 0;
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if (! i2c_reset())
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{
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puts("Can't reset I2C!\n");
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hang();
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}
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if (! cpc710_eeprom_checksum(sdram))
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{
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puts("Invalid EEPROM checksum !\n");
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hang();
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}
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rows = cpc710_eeprom_read(sdram, 3);
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cols = cpc710_eeprom_read(sdram, 4);
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/* Can be 2 or 4 banks; divide by 2
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*/
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banks2 = cpc710_eeprom_read(sdram, 17) / 2;
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lines = rows + cols + banks2;
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if (lines < 18 || lines > 26)
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{
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/* Unsupported configuration
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*/
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return 0;
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}
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mc |= cpc710_mcer_mem [lines - 18] << 6;
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for (i = 0; i < sizeof(cpc710_mem_org) / sizeof(cpc710_mem_org_t); i++)
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{
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cpc710_mem_org_t * corg = cpc710_mem_org + i;
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if (corg->rows == rows && corg->cols == cols && corg->banks2 == banks2)
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{
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org = corg;
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break;
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}
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}
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if (! org)
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{
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/* Unsupported configuration
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*/
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return 0;
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}
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mc |= (u32) org->org << 2;
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/* Supported configuration
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*/
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*mcer = mc;
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*size = 1l << (lines + 4);
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return 1;
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return (uint32_t)in_be32((unsigned *)(CPC710_SCA_CPC0 + addr));
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}
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static int cpc710_eeprom_checksum (
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unsigned int sdram)
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void
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sdram_init(void)
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{
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u8 sum = 0;
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unsigned int i;
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for (i = 0; i < 63; i++)
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{
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sum += cpc710_eeprom_read(sdram, i);
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}
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return sum == cpc710_eeprom_read(sdram, 63);
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cpc710_init();
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cpc710_pci_init();
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}
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static u8 cpc710_eeprom_read (
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unsigned int sdram,
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unsigned int offset)
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void
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cpc710_init(void)
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{
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u8 dev = (sdram << 1) | 0xa0;
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u8 data;
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setCPC710(CPC710_CPC0_RSTR, 0xf0000000);
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(void)getCPC710(CPC710_CPC0_MPSR);
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setCPC710(CPC710_CPC0_SIOC0, 0x00000000);
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setCPC710(CPC710_CPC0_PIDR, 0x00000000);
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setCPC710(CPC710_CPC0_UCTL, 0x00780000);
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setCPC710(CPC710_CPC0_ABCNTL, 0x00000000);
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setCPC710(CPC710_CPC0_SRST, 0x00000000);
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setCPC710(CPC710_CPC0_ERRC, 0x00000000);
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setCPC710(CPC710_CPC0_SESR, 0x00000000);
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setCPC710(CPC710_CPC0_SEAR, 0x00000000);
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setCPC710(CPC710_CPC0_PGCHP, 0x000000e0);
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setCPC710(CPC710_CPC0_GPDIR, 0x40000000);
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setCPC710(CPC710_CPC0_GPOUT, 0x40000000);
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setCPC710(CPC710_CPC0_ATAS, 0x709c2508);
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setCPC710(CPC710_CPC0_AVDG, 0x00000000);
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setCPC710(CPC710_SDRAM0_MESR, 0x00000000);
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setCPC710(CPC710_SDRAM0_MEAR, 0x00000000);
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setCPC710(CPC710_SDRAM0_MWPR, 0x00000000);
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setCPC710(CPC710_CPC0_RGBAN1, 0x00000000);
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if (! i2c_read_byte(& data, dev,offset))
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{
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puts("I2C error !\n");
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hang();
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}
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/*
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* Reset memory configuration
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*/
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setCPC710(CPC710_SDRAM0_MCER0, 0x00000000);
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setCPC710(CPC710_SDRAM0_MCER1, 0x00000000);
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setCPC710(CPC710_SDRAM0_MCER2, 0x00000000);
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setCPC710(CPC710_SDRAM0_MCER3, 0x00000000);
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setCPC710(CPC710_SDRAM0_MCER4, 0x00000000);
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setCPC710(CPC710_SDRAM0_MCER5, 0x00000000);
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setCPC710(CPC710_SDRAM0_MCER6, 0x00000000);
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setCPC710(CPC710_SDRAM0_MCER7, 0x00000000);
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setCPC710(CPC710_SDRAM0_MCCR, MCCR_DEFAULT);
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return data;
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/*
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* Temoporarily configure memory. This will be
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* replaced by i2c later.
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*/
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setCPC710(CPC710_SDRAM0_MCER0, 0x80000080);
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setCPC710(CPC710_SDRAM0_MCER1, 0x82000080);
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setCPC710(CPC710_SDRAM0_MCCR, 0xd2b06000);
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}
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@ -25,72 +25,98 @@
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#define _CPC710_H_
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/* Revision */
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#define CPC710_TYPE_100 0x80
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#define CPC710_TYPE_100 0x80
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#define CPC710_TYPE_100P 0x90
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/* System control area */
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#define HW_PHYS_SCA 0xff000000
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#define CPC710_PHYS_SCA 0xff000000
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#define HW_SCA_CPC0 0x000000
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#define HW_SCA_SDRAM0 0x000000
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#define HW_SCA_DMA0 0x1C0000
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#define CPC710_SCA_CPC0 0x000000
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#define CPC710_SCA_SDRAM0 0x000000
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#define CPC710_SCA_DMA0 0x1C0000
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#define HW_PHYS_CPC0 (HW_PHYS_SCA + HW_SCA_CPC0)
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#define HW_PHYS_SDRAM0 (HW_PHYS_SCA + HW_SCA_SDRAM0)
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#define CPC710_PHYS_CPC0 (CPC710_PHYS_SCA + CPC710_SCA_CPC0)
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#define CPC710_PHYS_SDRAM0 (CPC710_PHYS_SCA + CPC710_SCA_SDRAM0)
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#define HW_CPC0_PCICNFR 0x000c
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#define HW_CPC0_RSTR 0x0010
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#define HW_CPC0_SPOR 0x00e8
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#define HW_CPC0_UCTL 0x1000
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#define HW_CPC0_SIOC0 0x1020
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#define HW_CPC0_ABCNTL 0x1030
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#define HW_CPC0_SESR 0x1060
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#define HW_CPC0_SEAR 0x1070
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#define HW_CPC0_PGCHP 0x1100
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#define HW_CPC0_RGBAN0 0x1110
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#define HW_CPC0_RGBAN1 0x1120
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#define CPC710_CPC0_PIDR 0x0008
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#define CPC710_CPC0_PCICNFR 0x000c
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#define CPC710_CPC0_RSTR 0x0010
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#define CPC710_CPC0_SPOR 0x00e8
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#define CPC710_CPC0_UCTL 0x1000
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#define CPC710_CPC0_MPSR 0x1010
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#define CPC710_CPC0_SIOC0 0x1020
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#define CPC710_CPC0_ABCNTL 0x1030
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#define CPC710_CPC0_SRST 0x1040
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#define CPC710_CPC0_ERRC 0x1050
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#define CPC710_CPC0_SESR 0x1060
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#define CPC710_CPC0_SEAR 0x1070
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#define CPC710_CPC0_PGCHP 0x1100
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#define CPC710_CPC0_RGBAN0 0x1110
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#define CPC710_CPC0_RGBAN1 0x1120
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#define HW_CPC0_GPDIR 0x1130
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#define HW_CPC0_GPIN 0x1140
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#define HW_CPC0_GPOUT 0x1150
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#define CPC710_CPC0_GPDIR 0x1130
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#define CPC710_CPC0_GPIN 0x1140
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#define CPC710_CPC0_GPOUT 0x1150
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#define HW_CPC0_ATAS 0x1160
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#define CPC710_CPC0_ATAS 0x1160
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#define CPC710_CPC0_AVDG 0x1170
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#define HW_CPC0_PCIBAR 0x200018
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#define HW_CPC0_PCIENB 0x201000
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#define CPC710_CPC0_PCIBAR 0x200018
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#define CPC710_CPC0_PCIENB 0x201000
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#define HW_SDRAM0_MCCR 0x1200
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#define HW_SDRAM0_MESR 0x1220
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#define HW_SDRAM0_MEAR 0x1230
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#define CPC710_SDRAM0_MCCR 0x1200
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#define CPC710_SDRAM0_MWPR 0x1210
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#define CPC710_SDRAM0_MESR 0x1220
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#define CPC710_SDRAM0_MEAR 0x1230
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#define HW_SDRAM0_MCER0 0x1300
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#define HW_SDRAM0_MCER1 0x1310
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#define HW_SDRAM0_MCER2 0x1320
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#define HW_SDRAM0_MCER3 0x1330
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#define HW_SDRAM0_MCER4 0x1340
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#define HW_SDRAM0_MCER5 0x1350
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#define HW_SDRAM0_MCER6 0x1360
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#define HW_SDRAM0_MCER7 0x1370
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#define CPC710_SDRAM0_MCER0 0x1300
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#define CPC710_SDRAM0_MCER1 0x1310
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#define CPC710_SDRAM0_MCER2 0x1320
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#define CPC710_SDRAM0_MCER3 0x1330
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#define CPC710_SDRAM0_MCER4 0x1340
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#define CPC710_SDRAM0_MCER5 0x1350
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#define CPC710_SDRAM0_MCER6 0x1360
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#define CPC710_SDRAM0_MCER7 0x1370
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||||
#define HW_BRIDGE_PCIDG 0xf6120
|
||||
#define HW_BRIDGE_INTACK 0xf7700
|
||||
#define HW_BRIDGE_PIBAR 0xf7800
|
||||
#define HW_BRIDGE_PMBAR 0xf7810
|
||||
#define HW_BRIDGE_CRR 0xf7ef0
|
||||
#define HW_BRIDGE_PR 0xf7f20
|
||||
#define HW_BRIDGE_ACR 0xf7f30
|
||||
#define HW_BRIDGE_MSIZE 0xf7f40
|
||||
#define HW_BRIDGE_IOSIZE 0xf7f60
|
||||
#define HW_BRIDGE_SMBAR 0xf7f80
|
||||
#define HW_BRIDGE_SIBAR 0xf7fc0
|
||||
#define HW_BRIDGE_CFGADDR 0xf8000
|
||||
#define HW_BRIDGE_CFGDATA 0xf8010
|
||||
#define HW_BRIDGE_PSSIZE 0xf8100
|
||||
#define HW_BRIDGE_BARPS 0xf8120
|
||||
#define HW_BRIDGE_PSBAR 0xf8140
|
||||
#define CPC710_SDRAM0_SIOR0 0x1400
|
||||
#define CPC710_SDRAM0_SIOR1 0x1420
|
||||
|
||||
#define CPC710_BRIDGE_PSEA 0xf6110
|
||||
#define CPC710_BRIDGE_PCIDG 0xf6120
|
||||
#define CPC710_BRIDGE_INTACK 0xf7700
|
||||
#define CPC710_BRIDGE_PIBAR 0xf7800
|
||||
#define CPC710_BRIDGE_PMBAR 0xf7810
|
||||
#define CPC710_BRIDGE_CRR 0xf7ef0
|
||||
#define CPC710_BRIDGE_PR 0xf7f20
|
||||
#define CPC710_BRIDGE_ACR 0xf7f30
|
||||
#define CPC710_BRIDGE_MSIZE 0xf7f40
|
||||
#define CPC710_BRIDGE_IOSIZE 0xf7f60
|
||||
#define CPC710_BRIDGE_SMBAR 0xf7f80
|
||||
#define CPC710_BRIDGE_SIBAR 0xf7fc0
|
||||
#define CPC710_BRIDGE_CTLRW 0xf7fd0
|
||||
#define CPC710_BRIDGE_CFGADDR 0xf8000
|
||||
#define CPC710_BRIDGE_CFGDATA 0xf8010
|
||||
#define CPC710_BRIDGE_PSSIZE 0xf8100
|
||||
#define CPC710_BRIDGE_BARPS 0xf8120
|
||||
#define CPC710_BRIDGE_PSBAR 0xf8140
|
||||
#define CPC710_BRIDGE_BPMDLK 0xf8200
|
||||
#define CPC710_BRIDGE_TPMDLK 0xf8210
|
||||
#define CPC710_BRIDGE_BIODLK 0xf8220
|
||||
#define CPC710_BRIDGE_TIODLK 0xf8230
|
||||
#define CPC710_BRIDGE_INTSET 0xf8310
|
||||
|
||||
/* Configuration space registers */
|
||||
#define CPC710_BUS_NUMBER 0x40
|
||||
#define CPC710_SUB_BUS_NUMBER 0x41
|
||||
|
||||
/* MCCR register bits */
|
||||
#define CPC710_MCCR_DIAG_MODE 0x40000000
|
||||
#define CPC710_MCCR_ECC_DISABLE 0x08000000
|
||||
#define CPC710_MCCR_REFRESH_7CY 0x02000000
|
||||
#define CPC710_MCCR_DATA_MASK 0x00100000
|
||||
#define CPC710_MCCR_FIXED_BITS 0x00008000
|
||||
|
||||
extern void setCPC710(uint32_t, uint32_t);
|
||||
extern uint32_t getCPC710(uint32_t);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,309 +1,118 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <arch/io.h>
|
||||
#include "cpc710.h"
|
||||
#include "cpc710_pci.h"
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <pci.h>
|
||||
extern void setCPC710(uint32_t, uint32_t);
|
||||
|
||||
#include "hardware.h"
|
||||
#include "pcippc2.h"
|
||||
|
||||
struct pci_controller local_hose, cpci_hose;
|
||||
|
||||
static u32 cpc710_mapped_ram;
|
||||
|
||||
/* Enable PCI retry timeouts
|
||||
*/
|
||||
void cpc710_pci_enable_timeout (void)
|
||||
void
|
||||
setCPC710PCI32_16(uint32_t addr, uint16_t data)
|
||||
{
|
||||
out32(BRIDGE(LOCAL, CFGADDR), 0x50000080);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(LOCAL, CFGDATA), 0x32000000);
|
||||
iobarrier_rw();
|
||||
|
||||
out32(BRIDGE(CPCI, CFGADDR), 0x50000180);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(CPCI, CFGDATA), 0x32000000);
|
||||
iobarrier_rw();
|
||||
out_le16((unsigned short *)(CPC710_BRIDGE_CPCI_PHYS + addr), data);
|
||||
}
|
||||
|
||||
void cpc710_pci_init (void)
|
||||
void
|
||||
setCPC710PCI32_32(uint32_t addr, uint32_t data)
|
||||
{
|
||||
u32 sdram_size = pcippc2_sdram_size();
|
||||
|
||||
cpc710_mapped_ram = sdram_size < PCI_MEMORY_MAXSIZE ?
|
||||
sdram_size : PCI_MEMORY_MAXSIZE;
|
||||
|
||||
/* Select the local PCI
|
||||
*/
|
||||
out32(REG(CPC0, PCICNFR), 0x80000002);
|
||||
iobarrier_rw();
|
||||
|
||||
out32(REG(CPC0, PCIBAR), BRIDGE_LOCAL_PHYS);
|
||||
iobarrier_rw();
|
||||
|
||||
/* Enable PCI bridge address decoding
|
||||
*/
|
||||
out32(REG(CPC0, PCIENB), 0x80000000);
|
||||
iobarrier_rw();
|
||||
|
||||
/* Select the CPCI bridge
|
||||
*/
|
||||
out32(REG(CPC0, PCICNFR), 0x80000003);
|
||||
iobarrier_rw();
|
||||
|
||||
out32(REG(CPC0, PCIBAR), BRIDGE_CPCI_PHYS);
|
||||
iobarrier_rw();
|
||||
|
||||
/* Enable PCI bridge address decoding
|
||||
*/
|
||||
out32(REG(CPC0, PCIENB), 0x80000000);
|
||||
iobarrier_rw();
|
||||
|
||||
/* Disable configuration accesses
|
||||
*/
|
||||
out32(REG(CPC0, PCICNFR), 0x80000000);
|
||||
iobarrier_rw();
|
||||
|
||||
/* Initialise the local PCI
|
||||
*/
|
||||
out32(BRIDGE(LOCAL, CRR), 0x7c000000);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(LOCAL, PCIDG), 0x40000000);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(LOCAL, PIBAR), BRIDGE_LOCAL_IO_BUS);
|
||||
out32(BRIDGE(LOCAL, SIBAR), BRIDGE_LOCAL_IO_PHYS);
|
||||
out32(BRIDGE(LOCAL, IOSIZE), -BRIDGE_LOCAL_IO_SIZE);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(LOCAL, PMBAR), BRIDGE_LOCAL_MEM_BUS);
|
||||
out32(BRIDGE(LOCAL, SMBAR), BRIDGE_LOCAL_MEM_PHYS);
|
||||
out32(BRIDGE(LOCAL, MSIZE), -BRIDGE_LOCAL_MEM_SIZE);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(LOCAL, PR), 0x00ffe000);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(LOCAL, ACR), 0xfe000000);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(LOCAL, PSBAR), PCI_MEMORY_BUS >> 24);
|
||||
out32(BRIDGE(LOCAL, BARPS), PCI_MEMORY_PHYS >> 24);
|
||||
out32(BRIDGE(LOCAL, PSSIZE), 256 - (cpc710_mapped_ram >> 24));
|
||||
iobarrier_rw();
|
||||
|
||||
/* Initialise the CPCI bridge
|
||||
*/
|
||||
out32(BRIDGE(CPCI, CRR), 0x7c000000);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(CPCI, PCIDG), 0xC0000000);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(CPCI, PIBAR), BRIDGE_CPCI_IO_BUS);
|
||||
out32(BRIDGE(CPCI, SIBAR), BRIDGE_CPCI_IO_PHYS);
|
||||
out32(BRIDGE(CPCI, IOSIZE), -BRIDGE_CPCI_IO_SIZE);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(CPCI, PMBAR), BRIDGE_CPCI_MEM_BUS);
|
||||
out32(BRIDGE(CPCI, SMBAR), BRIDGE_CPCI_MEM_PHYS);
|
||||
out32(BRIDGE(CPCI, MSIZE), -BRIDGE_CPCI_MEM_SIZE);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(CPCI, PR), 0x80ffe000);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(CPCI, ACR), 0xdf000000);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(CPCI, PSBAR), PCI_MEMORY_BUS >> 24);
|
||||
out32(BRIDGE(CPCI, BARPS), PCI_MEMORY_PHYS >> 24);
|
||||
out32(BRIDGE(CPCI, PSSIZE), 256 - (cpc710_mapped_ram >> 24));
|
||||
iobarrier_rw();
|
||||
|
||||
/* Local PCI
|
||||
*/
|
||||
|
||||
out32(BRIDGE(LOCAL, CFGADDR), 0x04000080);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(LOCAL, CFGDATA), 0x56010000);
|
||||
iobarrier_rw();
|
||||
|
||||
out32(BRIDGE(LOCAL, CFGADDR), 0x0c000080);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(LOCAL, CFGDATA), PCI_LATENCY_TIMER_VAL << 16);
|
||||
iobarrier_rw();
|
||||
|
||||
/* Set bus and subbus numbers
|
||||
*/
|
||||
out32(BRIDGE(LOCAL, CFGADDR), 0x40000080);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(LOCAL, CFGDATA), 0x00000000);
|
||||
iobarrier_rw();
|
||||
|
||||
out32(BRIDGE(LOCAL, CFGADDR), 0x50000080);
|
||||
iobarrier_rw();
|
||||
/* PCI retry timeouts will be enabled later
|
||||
*/
|
||||
out32(BRIDGE(LOCAL, CFGDATA), 0x00000000);
|
||||
iobarrier_rw();
|
||||
|
||||
/* CPCI
|
||||
*/
|
||||
|
||||
/* Set bus and subbus numbers
|
||||
*/
|
||||
out32(BRIDGE(CPCI, CFGADDR), 0x40000080);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(CPCI, CFGDATA), 0x01010000);
|
||||
iobarrier_rw();
|
||||
|
||||
out32(BRIDGE(CPCI, CFGADDR), 0x04000180);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(CPCI, CFGDATA), 0x56010000);
|
||||
iobarrier_rw();
|
||||
|
||||
out32(BRIDGE(CPCI, CFGADDR), 0x0c000180);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(CPCI, CFGDATA), PCI_LATENCY_TIMER_VAL << 16);
|
||||
iobarrier_rw();
|
||||
|
||||
/* Write to the PSBAR */
|
||||
out32(BRIDGE(CPCI, CFGADDR), 0x10000180);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(CPCI, CFGDATA), cpu_to_le32(PCI_MEMORY_BUS));
|
||||
iobarrier_rw();
|
||||
|
||||
/* Set bus and subbus numbers
|
||||
*/
|
||||
out32(BRIDGE(CPCI, CFGADDR), 0x40000180);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(CPCI, CFGDATA), 0x01ff0000);
|
||||
iobarrier_rw();
|
||||
|
||||
out32(BRIDGE(CPCI, CFGADDR), 0x50000180);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(CPCI, CFGDATA), 0x32000000);
|
||||
/* PCI retry timeouts will be enabled later
|
||||
*/
|
||||
out32(BRIDGE(CPCI, CFGDATA), 0x00000000);
|
||||
iobarrier_rw();
|
||||
|
||||
/* Remove reset on the PCI buses
|
||||
*/
|
||||
out32(BRIDGE(LOCAL, CRR), 0xfc000000);
|
||||
iobarrier_rw();
|
||||
out32(BRIDGE(CPCI, CRR), 0xfc000000);
|
||||
iobarrier_rw();
|
||||
|
||||
local_hose.first_busno = 0;
|
||||
local_hose.last_busno = 0xff;
|
||||
|
||||
/* System memory space */
|
||||
pci_set_region(local_hose.regions + 0,
|
||||
PCI_MEMORY_BUS,
|
||||
PCI_MEMORY_PHYS,
|
||||
PCI_MEMORY_MAXSIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
/* PCI memory space */
|
||||
pci_set_region(local_hose.regions + 1,
|
||||
BRIDGE_LOCAL_MEM_BUS,
|
||||
BRIDGE_LOCAL_MEM_PHYS,
|
||||
BRIDGE_LOCAL_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* PCI I/O space */
|
||||
pci_set_region(local_hose.regions + 2,
|
||||
BRIDGE_LOCAL_IO_BUS,
|
||||
BRIDGE_LOCAL_IO_PHYS,
|
||||
BRIDGE_LOCAL_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
local_hose.region_count = 3;
|
||||
|
||||
pci_setup_indirect(&local_hose,
|
||||
BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGADDR,
|
||||
BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGDATA);
|
||||
|
||||
pci_register_hose(&local_hose);
|
||||
|
||||
/* Initialize PCI32 bus registers */
|
||||
pci_hose_write_config_byte(&local_hose,
|
||||
PCI_BDF(local_hose.first_busno,0,0),
|
||||
CPC710_BUS_NUMBER,
|
||||
local_hose.first_busno);
|
||||
pci_hose_write_config_byte(&local_hose,
|
||||
PCI_BDF(local_hose.first_busno,0,0),
|
||||
CPC710_SUB_BUS_NUMBER,
|
||||
local_hose.last_busno);
|
||||
|
||||
local_hose.last_busno = pci_hose_scan(&local_hose);
|
||||
|
||||
/* Write out correct max subordinate bus number for local hose */
|
||||
pci_hose_write_config_byte(&local_hose,
|
||||
PCI_BDF(local_hose.first_busno,0,0),
|
||||
CPC710_SUB_BUS_NUMBER,
|
||||
local_hose.last_busno);
|
||||
|
||||
cpci_hose.first_busno = local_hose.last_busno + 1;
|
||||
cpci_hose.last_busno = 0xff;
|
||||
|
||||
/* System memory space */
|
||||
pci_set_region(cpci_hose.regions + 0,
|
||||
PCI_MEMORY_BUS,
|
||||
PCI_MEMORY_PHYS,
|
||||
PCI_MEMORY_MAXSIZE,
|
||||
PCI_REGION_MEMORY);
|
||||
|
||||
/* PCI memory space */
|
||||
pci_set_region(cpci_hose.regions + 1,
|
||||
BRIDGE_CPCI_MEM_BUS,
|
||||
BRIDGE_CPCI_MEM_PHYS,
|
||||
BRIDGE_CPCI_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* PCI I/O space */
|
||||
pci_set_region(cpci_hose.regions + 2,
|
||||
BRIDGE_CPCI_IO_BUS,
|
||||
BRIDGE_CPCI_IO_PHYS,
|
||||
BRIDGE_CPCI_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
cpci_hose.region_count = 3;
|
||||
|
||||
pci_setup_indirect(&cpci_hose,
|
||||
BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGADDR,
|
||||
BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGDATA);
|
||||
|
||||
pci_register_hose(&cpci_hose);
|
||||
|
||||
/* Initialize PCI64 bus registers */
|
||||
pci_hose_write_config_byte(&cpci_hose,
|
||||
PCI_BDF(cpci_hose.first_busno,0,0),
|
||||
CPC710_BUS_NUMBER,
|
||||
cpci_hose.first_busno);
|
||||
pci_hose_write_config_byte(&cpci_hose,
|
||||
PCI_BDF(cpci_hose.first_busno,0,0),
|
||||
CPC710_SUB_BUS_NUMBER,
|
||||
cpci_hose.last_busno);
|
||||
|
||||
cpci_hose.last_busno = pci_hose_scan(&cpci_hose);
|
||||
|
||||
/* Write out correct max subordinate bus number for cpci hose */
|
||||
pci_hose_write_config_byte(&cpci_hose,
|
||||
PCI_BDF(cpci_hose.first_busno,0,0),
|
||||
CPC710_SUB_BUS_NUMBER,
|
||||
cpci_hose.last_busno);
|
||||
out_le32((unsigned *)(CPC710_BRIDGE_CPCI_PHYS + addr), data);
|
||||
}
|
||||
|
||||
void
|
||||
setCPC710PCI64_16(uint16_t addr, uint16_t data)
|
||||
{
|
||||
out_le16((unsigned short *)(CPC710_BRIDGE_LOCAL_PHYS + addr), data);
|
||||
}
|
||||
|
||||
void
|
||||
setCPC710PCI64_32(uint32_t addr, uint32_t data)
|
||||
{
|
||||
out_le32((unsigned *)(CPC710_BRIDGE_LOCAL_PHYS + addr), data);
|
||||
}
|
||||
|
||||
void
|
||||
cpc710_pci_init(void)
|
||||
{
|
||||
/* Enable PCI32 */
|
||||
setCPC710(CPC710_CPC0_PCICNFR, 0x80000002); /* activate PCI32 config */
|
||||
setCPC710(CPC710_CPC0_PCIBAR, CPC710_BRIDGE_CPCI_PHYS); /* PCI32 base address */
|
||||
setCPC710(CPC710_CPC0_PCIENB, 0x80000000); /* enable addr space */
|
||||
setCPC710(CPC710_CPC0_PCICNFR, 0x00000000); /* config done */
|
||||
|
||||
/* Reset PCI Status register */
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_CFGADDR, 0x80000006);
|
||||
setCPC710PCI32_16(CPC710_BRIDGE_CFGDATA, 0xffff);
|
||||
|
||||
/* Configure bus number */
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_CFGADDR, 0x80000040);
|
||||
setCPC710PCI32_16(CPC710_BRIDGE_CFGDATA, 0x0000);
|
||||
|
||||
/* Set PCI configuration registers */
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_PCIDG, 0x40000000);
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_PIBAR, 0x00000000);
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_PMBAR, 0x00000000);
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_PR, 0xa000c000);
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_ACR, 0xfc000000);
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_MSIZE, 0xf8000000); /* 128Mb */
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_IOSIZE, 0xf8000000); /* 128Mb */
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_SMBAR, 0xc0000000);
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_SIBAR, 0x80000000);
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_CTLRW, 0x00000000);
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_PSSIZE, 0x00000080);
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_BARPS, 0x00000000);
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_PSBAR, 0x00000080);
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_BPMDLK, 0x00000000);
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_TPMDLK, 0x00000000);
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_BIODLK, 0x00000000);
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_TIODLK, 0x00000000);
|
||||
|
||||
/* Enable address space */
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_CFGADDR, 0x80000004);
|
||||
setCPC710PCI32_16(CPC710_BRIDGE_CFGDATA, 0xfda7);
|
||||
|
||||
setCPC710PCI32_32(CPC710_BRIDGE_CRR, 0xfc000000);
|
||||
|
||||
/* Enable PCI64 */
|
||||
setCPC710(CPC710_CPC0_PCICNFR, 0x80000003); /* activate PCI64 config */
|
||||
setCPC710(CPC710_CPC0_PCIBAR, CPC710_BRIDGE_LOCAL_PHYS); /* PCI64 base address */
|
||||
setCPC710(CPC710_CPC0_PCIENB, 0x80000000); /* enable addr space */
|
||||
setCPC710(CPC710_CPC0_PCICNFR, 0x00000000); /* config done */
|
||||
|
||||
/* Reset PCI Status register */
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80000006);
|
||||
setCPC710PCI64_16(CPC710_BRIDGE_CFGDATA, 0xffff);
|
||||
|
||||
/* Reset G_INT[A-D] bits in INT_RESET */
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80000068);
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_CFGDATA, 0x0000000f);
|
||||
|
||||
/* Configure bus number BUSNO=1, SUBNO=1 */
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80000040);
|
||||
setCPC710PCI64_16(CPC710_BRIDGE_CFGDATA, 0x0101);
|
||||
|
||||
/* Set PCI configuration registers */
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_PSEA, 0x00000000);
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_PCIDG, 0xc0000000);
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_PIBAR, 0x00000000);
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_PMBAR, 0x00000000);
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_PR, 0x80008000);
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_ACR, 0xff000000);
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_MSIZE, 0xf8000000); /* 128Mb */
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_IOSIZE, 0xf8000000); /* 128Mb */
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_SMBAR, 0xc8000000);
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_SIBAR, 0x88000000);
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_CTLRW, 0x02000000);
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_PSSIZE, 0x00000080);
|
||||
|
||||
/* Config PSBAR for PCI64 */
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80000010);
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_CFGDATA, 0x80000000);
|
||||
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_BARPS, 0x00000000);
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_INTSET, 0x00000000);
|
||||
|
||||
/* Enable address space */
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_CFGADDR, 0x80010004);
|
||||
setCPC710PCI64_16(CPC710_BRIDGE_CFGDATA, 0xfda7);
|
||||
|
||||
setCPC710PCI64_32(CPC710_BRIDGE_CRR, 0xfc000000);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,28 +24,24 @@
|
|||
#ifndef _CPC710_PCI_H_
|
||||
#define _CPC710_PCI_H_
|
||||
|
||||
#define PCI_MEMORY_PHYS 0x00000000
|
||||
#define PCI_MEMORY_BUS 0x80000000
|
||||
#define PCI_MEMORY_MAXSIZE 0x20000000
|
||||
#define CPC710_PCI_MEMORY_PHYS 0x00000000
|
||||
#define CPC710_PCI_MEMORY_BUS 0x80000000
|
||||
#define CPC710_PCI_MEMORY_MAXSIZE 0x20000000
|
||||
|
||||
#define BRIDGE_CPCI_PHYS 0xff500000
|
||||
#define BRIDGE_CPCI_MEM_SIZE 0x08000000
|
||||
#define BRIDGE_CPCI_MEM_PHYS 0xf0000000
|
||||
#define BRIDGE_CPCI_MEM_BUS 0x00000000
|
||||
#define BRIDGE_CPCI_IO_SIZE 0x02000000
|
||||
#define BRIDGE_CPCI_IO_PHYS 0xfc000000
|
||||
#define BRIDGE_CPCI_IO_BUS 0x00000000
|
||||
#define CPC710_BRIDGE_CPCI_PHYS 0xff500000
|
||||
#define CPC710_BRIDGE_CPCI_MEM_SIZE 0x08000000
|
||||
#define CPC710_BRIDGE_CPCI_MEM_PHYS 0xf0000000
|
||||
#define CPC710_BRIDGE_CPCI_MEM_BUS 0x00000000
|
||||
#define CPC710_BRIDGE_CPCI_IO_SIZE 0x02000000
|
||||
#define CPC710_BRIDGE_CPCI_IO_PHY 0xfc000000
|
||||
#define CPC710_BRIDGE_CPCI_IO_BUS 0x00000000
|
||||
|
||||
#define BRIDGE_LOCAL_PHYS 0xff400000
|
||||
#define BRIDGE_LOCAL_MEM_SIZE 0x04000000
|
||||
#define BRIDGE_LOCAL_MEM_PHYS 0xf8000000
|
||||
#define BRIDGE_LOCAL_MEM_BUS 0x40000000
|
||||
#define BRIDGE_LOCAL_IO_SIZE 0x01000000
|
||||
#define BRIDGE_LOCAL_IO_PHYS 0xfe000000
|
||||
#define BRIDGE_LOCAL_IO_BUS 0x04000000
|
||||
|
||||
#define BRIDGE(r, x) (BRIDGE_##r##_PHYS + HW_BRIDGE_##x)
|
||||
|
||||
#define PCI_LATENCY_TIMER_VAL 0xff
|
||||
#define CPC710_BRIDGE_LOCAL_PHYS 0xff400000
|
||||
#define CPC710_BRIDGE_LOCAL_MEM_SIZE 0x04000000
|
||||
#define CPC710_BRIDGE_LOCAL_MEM_PHYS 0xf8000000
|
||||
#define CPC710_BRIDGE_LOCAL_MEM_BUS 0x40000000
|
||||
#define CPC710_BRIDGE_LOCAL_IO_SIZE 0x01000000
|
||||
#define CPC710_BRIDGE_LOCAL_IO_PHYS 0xfe000000
|
||||
#define CPC710_BRIDGE_LOCAL_IO_BUS 0x04000000
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue