diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 6be69fe2ee..361e563cab 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -127,6 +127,7 @@ chip soc/intel/tigerlake
 
 	# TCSS USB3
 	register "TcssXhciEn" = "1"
+	register "TcssAuxOri" = "0"
 
 	# DP port
 	register "DdiPortAConfig" = "1"	# eDP
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 8fd9087c7f..6cef4f84a6 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -103,6 +103,9 @@ chip soc/intel/tigerlake
 		[PchSerialIoIndexUART2] = PchSerialIoPci,
 	}"
 
+	# TCSS USB3
+	register "TcssAuxOri" = "0"
+
 	#HD Audio
 	register "PchHdaDspEnable" = "1"
 	register "PchHdaAudioLinkHdaEnable" = "0"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 4ff35cc437..c5cc800224 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -99,6 +99,9 @@ chip soc/intel/tigerlake
 		[PchSerialIoIndexUART2] = PchSerialIoPci,
 	}"
 
+	# TCSS USB3
+	register "TcssAuxOri" = "0"
+
 	#HD Audio
 	register "PchHdaDspEnable" = "1"
 	register "PchHdaAudioLinkHdaEnable" = "0"