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mb/google/brya/var/kano: Correct GPIO GPP_R6 and GPP_R7 setting 

Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1).

BUG=b:202913826
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ibf8ff0e48c4bab435d082dee27bcd53bc85b088d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CT Lin <ctlin0@nuvoton.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
David Wu 2021-10-18 16:39:02 +08:00 committed by Felix Held
parent e2c6d9c7cb
commit 91e8c2a1d4
2 changed files with 4 additions and 4 deletions
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4
src/mainboard/google/brya/variants/kano/fw_config.c
View File

@ -8,8 +8,8 @@
static const struct pad_config dmic_enable_pads[] = { static const struct pad_config dmic_enable_pads[] = {
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* DMIC_CLK1_R */
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* DMIC_DATA1_R */
}; };
static const struct pad_config dmic_disable_pads[] = { static const struct pad_config dmic_disable_pads[] = {

4
src/mainboard/google/brya/variants/kano/gpio.c
View File

@ -82,9 +82,9 @@ static const struct pad_config override_gpio_table[] = {
/* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
/* R6 : I2S2_TXD ==> DMIC_CLK1_R */ /* R6 : I2S2_TXD ==> DMIC_CLK1_R */
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
/* R7 : I2S2_RXD ==> DMIC_DATA1_R */ /* R7 : I2S2_RXD ==> DMIC_DATA1_R */
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
/* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */ /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2),