From 91ef21df62b8dd44c3bfb551a426ed949c5b2eb4 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Fri, 15 Jul 2016 14:44:48 -0700 Subject: [PATCH] soc/intel/apollolake: Implement reset_prepare() At first boot CSE spends long time preparing media for use. As result it may not be able to deal with a CPU reset. Add reset_prepare() callback that polls CSE readiness. BUG=chrome-os-partner:55055 TEST=build with release version of fsp, reboot, observe polling for CSE, then proper reboot happening Change-Id: I639ef900b97132f1a7f269bb864d70009df9fdfe Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/15721 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/reset.c | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c index 644d88d882..f759bac06b 100644 --- a/src/soc/intel/apollolake/reset.c +++ b/src/soc/intel/apollolake/reset.c @@ -13,11 +13,47 @@ * GNU General Public License for more details. */ +#include +#include #include +#include #include +#include + +#define CSE_WAIT_MAX_MS 1000 void global_reset(void) { global_reset_enable(1); hard_reset(); } + +void reset_prepare(void) +{ + struct stopwatch sw; + + /* + * If CSE state is something else than 'normal', it is probably in some + * recovery state. In this case there is no point in waiting for it to + * get ready so we cross fingers and reset. + */ + if (!heci_cse_normal()) { + printk(BIOS_DEBUG, "CSE is not in normal state, resetting\n"); + return; + } + + /* Reset if CSE is ready */ + if (heci_cse_done()) + return; + + printk(BIOS_SPEW, "CSE is not yet ready, waiting\n"); + stopwatch_init_msecs_expire(&sw, CSE_WAIT_MAX_MS); + while (!heci_cse_done()) { + if (stopwatch_expired(&sw)) { + printk(BIOS_SPEW, "CSE timed out. Resetting\n"); + return; + } + mdelay(1); + } + printk(BIOS_SPEW, "CSE took %lu ms\n", stopwatch_duration_msecs(&sw)); +}