soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_UART

Since the functions that get called by the coreboot console
initialization code aren't in the SOC-specific code anymore, the SOC's
uart.c can be included unconditionally in the build now. This also
replaces the STONEYRIDGE_UART Kconfig option with the common
AMD_SOC_CONSOLE_UART one.

Change-Id: I09c15566a402895d6388715e8e5a802dc3c94fdd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49375
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/kahlee/Kconfig

@@ -19,7 +19,7 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select MAINBOARD_HAS_CHROMEOS
 	select SERIRQ_CONTINUOUS_MODE
-	select STONEYRIDGE_UART
+	select AMD_SOC_CONSOLE_UART
 	select SOC_AMD_SMU_FANLESS
 	select HAVE_ACPI_RESUME
 	select DRIVERS_GENERIC_BH720

src/soc/amd/stoneyridge/Kconfig

@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_SMBUS
 	select SOC_AMD_COMMON_BLOCK_SMI
 	select SOC_AMD_COMMON_BLOCK_SPI
+	select SOC_AMD_COMMON_BLOCK_UART
 	select SSE2
 	select TSC_SYNC_LFENCE
 	select X86_AMD_FIXED_MTRRS
@@ -258,20 +259,6 @@ config STONEYRIDGE_ACPI_IO_BASE
 	  Base address for the ACPI registers.
 	  This value must match the hardcoded value of AGESA.
 
-config STONEYRIDGE_UART
-	bool "UART controller on Stoney Ridge"
-	default n
-	select DRIVERS_UART_8250MEM
-	select DRIVERS_UART_8250MEM_32
-	select NO_UART_ON_SUPERIO
-	select UART_OVERRIDE_REFCLK
-	help
-	  There are two UART controllers in Stoney Ridge.
-	  The UART registers are memory-mapped. UART
-	  controller 0 registers range from FEDC_6000h
-	  to FEDC_6FFFh. UART controller 1 registers
-	  range from FEDC_8000h to FEDC_8FFFh.
-
 config CONSOLE_UART_BASE_ADDRESS
 	depends on CONSOLE_SERIAL
 	hex

src/soc/amd/stoneyridge/Makefile.inc

@@ -10,7 +10,7 @@ subdirs-y += ../../../cpu/x86/mtrr
 subdirs-y += ../../../cpu/x86/pae
 subdirs-y += ../../../cpu/x86/smm
 
-bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
+bootblock-y += uart.c
 bootblock-y += BiosCallOuts.c
 bootblock-y += bootblock.c
 bootblock-y += gpio.c
@@ -28,7 +28,7 @@ romstage-y += gpio.c
 romstage-y += monotonic_timer.c
 romstage-y += smbus_spd.c
 romstage-y += memmap.c
-romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
+romstage-y += uart.c
 romstage-y += tsc_freq.c
 romstage-y += southbridge.c
 romstage-y += psp.c
@@ -36,11 +36,11 @@ romstage-y += psp.c
 verstage-y += gpio.c
 verstage-y += i2c.c
 verstage-y += monotonic_timer.c
-verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
+verstage-y += uart.c
 verstage-y += tsc_freq.c
 
 postcar-y += monotonic_timer.c
-postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
+postcar-y += uart.c
 postcar-y += memmap.c
 postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c
 postcar-y += tsc_freq.c
@@ -59,7 +59,7 @@ ramstage-y += northbridge.c
 ramstage-y += sata.c
 ramstage-y += memmap.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
-ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
+ramstage-y += uart.c
 ramstage-y += usb.c
 ramstage-y += tsc_freq.c
 ramstage-y += finalize.c

src/soc/amd/stoneyridge/bootblock.c

@@ -89,7 +89,7 @@ void bootblock_soc_early_init(void)
 
 void bootblock_soc_init(void)
 {
-	if (CONFIG(STONEYRIDGE_UART))
+	if (CONFIG(AMD_SOC_CONSOLE_UART))
 		assert(CONFIG_UART_FOR_CONSOLE >= 0
 					&& CONFIG_UART_FOR_CONSOLE <= 1);
 

src/soc/amd/stoneyridge/uart.c

@@ -1,17 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <console/uart.h>
+#include <amdblocks/uart.h>
 #include <soc/southbridge.h>
+#include <types.h>
 
-uintptr_t uart_platform_base(unsigned int idx)
+uintptr_t get_uart_base(unsigned int idx)
 {
 	if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1)
 		return 0;
 
 	return (uintptr_t)(APU_UART0_BASE + 0x2000 * (idx & 1));
 }
-
-unsigned int uart_platform_refclk(void)
-{
-	return 48000000;
-}