brya: add new zydron variant
Add a new zydron variant, which is a variant of brya's skolas baseboard. currently copy the variant file from kano. BUG=b:250787251 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I49a41678568daef80b7cd1e3ed60ce4763034f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68130 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
David Wu
Nick Vaccaro
parent
e8bb6d2b16
commit
91fb8ca7e7
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@ -144,6 +144,7 @@ config DRIVER_TPM_I2C_BUS
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default 0x0 if BOARD_GOOGLE_PUJJO
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default 0x0 if BOARD_GOOGLE_XIVU
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default 0x0 if BOARD_GOOGLE_YAVIKS
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default 0x1 if BOARD_GOOGLE_ZYDRON
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config DRIVER_TPM_I2C_ADDR
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hex
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@ -210,6 +211,7 @@ config MAINBOARD_PART_NUMBER
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default "Gaelin4ADL" if BOARD_GOOGLE_GAELIN4ADL
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default "Yaviks" if BOARD_GOOGLE_YAVIKS
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default "Lisbon" if BOARD_GOOGLE_LISBON
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default "Zydron" if BOARD_GOOGLE_ZYDRON
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config VARIANT_DIR
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default "brya0" if BOARD_GOOGLE_BRYA0
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@ -248,6 +250,7 @@ config VARIANT_DIR
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default "gaelin" if BOARD_GOOGLE_GAELIN4ADL
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default "yaviks" if BOARD_GOOGLE_YAVIKS
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default "lisbon" if BOARD_GOOGLE_LISBON
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default "zydron" if BOARD_GOOGLE_ZYDRON
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config VBOOT
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select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA
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@ -282,7 +285,7 @@ config USE_PM_ACPI_TIMER
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choice
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prompt "Cache as RAM (CAR) setup configuration to use"
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default USE_ADL_NEM if BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID || BOARD_GOOGLE_CRAASK || BOARD_GOOGLE_SKOLAS || BOARD_GOOGLE_SKOLAS4ES || BOARD_GOOGLE_JOXER || BOARD_GOOGLE_PUJJO || BOARD_GOOGLE_XIVU || BOARD_GOOGLE_YAVIKS
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default USE_ADL_NEM if BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID || BOARD_GOOGLE_CRAASK || BOARD_GOOGLE_SKOLAS || BOARD_GOOGLE_SKOLAS4ES || BOARD_GOOGLE_JOXER || BOARD_GOOGLE_PUJJO || BOARD_GOOGLE_XIVU || BOARD_GOOGLE_YAVIKS || BOARD_GOOGLE_ZYDRON
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default USE_ADL_ENEM
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config USE_ADL_ENEM
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@ -273,3 +273,11 @@ config BOARD_GOOGLE_LISBON
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bool "-> Lisbon"
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select BOARD_GOOGLE_BASEBOARD_BRASK
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select DRIVERS_GENESYSLOGIC_GL9750
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config BOARD_GOOGLE_ZYDRON
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bool "-> Zydron"
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select BOARD_GOOGLE_BASEBOARD_SKOLAS
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select DRIVERS_I2C_MAX98373
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select DRIVERS_I2C_NAU8825
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select DRIVERS_INTEL_MIPI_CAMERA
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select SOC_INTEL_COMMON_BLOCK_IPU
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@ -0,0 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-$(CONFIG_FW_CONFIG) += variant.c
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ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
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ramstage-y += ramstage.c
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@ -0,0 +1,87 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootstate.h>
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#include <console/console.h>
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#include <fw_config.h>
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#include <gpio.h>
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static const struct pad_config dmic_enable_pads[] = {
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PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */
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PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */
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PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */
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PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */
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};
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static const struct pad_config dmic_disable_pads[] = {
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PAD_NC(GPP_R4, NONE),
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PAD_NC(GPP_R5, NONE),
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PAD_NC(GPP_R6, NONE),
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PAD_NC(GPP_R7, NONE),
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};
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static const struct pad_config i2s_enable_pads[] = {
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */
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PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */
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PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */
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PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */
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PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */
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PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */
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PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */
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PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */
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};
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static const struct pad_config i2s_disable_pads[] = {
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PAD_NC(GPP_R0, NONE),
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PAD_NC(GPP_R1, NONE),
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PAD_NC(GPP_R2, NONE),
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PAD_NC(GPP_R3, NONE),
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PAD_NC(GPP_S0, NONE),
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PAD_NC(GPP_S1, NONE),
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PAD_NC(GPP_S2, NONE),
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PAD_NC(GPP_S3, NONE),
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};
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static const struct pad_config bt_i2s_enable_pads[] = {
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PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */
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PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */
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PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */
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PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */
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PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */
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PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */
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PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */
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PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */
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};
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static const struct pad_config bt_i2s_disable_pads[] = {
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PAD_NC(GPP_VGPIO_30, NONE),
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PAD_NC(GPP_VGPIO_31, NONE),
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PAD_NC(GPP_VGPIO_32, NONE),
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PAD_NC(GPP_VGPIO_33, NONE),
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PAD_NC(GPP_VGPIO_34, NONE),
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PAD_NC(GPP_VGPIO_35, NONE),
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PAD_NC(GPP_VGPIO_36, NONE),
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PAD_NC(GPP_VGPIO_37, NONE),
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};
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static void fw_config_handle(void *unused)
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{
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if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
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printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
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gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
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gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
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gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
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return;
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}
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if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_NAU88L25B_I2S))) {
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printk(BIOS_INFO, "Configure audio over I2S with MAX98373 NAU88L25B.\n");
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gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
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gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
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printk(BIOS_INFO, "BT offload enabled\n");
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gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
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} else {
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printk(BIOS_INFO, "BT offload disabled\n");
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gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
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}
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
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@ -0,0 +1,196 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* A6 : ESPI_ALERT1# ==> NC */
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PAD_NC(GPP_A6, NONE),
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/* A7 : SRCCLK_OE7# ==> NC */
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PAD_NC(GPP_A7, NONE),
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/* A8 : SRCCLKREQ7# ==> NC */
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PAD_NC(GPP_A8, NONE),
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/* A12 : SATAXPCIE1 ==> NC */
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PAD_NC(GPP_A12, NONE),
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/* A15 : USB_OC2# ==> NC */
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PAD_NC(GPP_A15, NONE),
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/* A19 : DDSP_HPD1 ==> NC */
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PAD_NC(GPP_A19, NONE),
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/* A20 : DDSP_HPD2 ==> NC */
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PAD_NC(GPP_A20, NONE),
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/* A21 : DDPC_CTRCLK ==> NC */
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PAD_NC(GPP_A21, NONE),
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/* A22 : DDPC_CTRLDATA ==> NC */
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PAD_NC(GPP_A22, NONE),
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/* D3 : ISH_GP3 ==> NC */
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PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
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/* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
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/* D6 : SRCCLKREQ1# ==> APU_PEN_DETECT_ODL */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_D6, NONE, PLTRST),
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/* D7 : SRCCLKREQ2# ==> NC */
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PAD_NC(GPP_D7, NONE),
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/* D8 : SRCCLKREQ3# ==> NC */
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PAD_NC(GPP_D8, NONE),
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/* D16 : ISH_UART0_CTS# ==> PEN_PWR_EN */
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PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG),
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/* D17 : UART1_RXD ==> APU_PEN_DETECT_ODL */
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PAD_CFG_GPI_SCI_LOCK(GPP_D17, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG),
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/* D18 : UART1_TXD ==> NC */
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PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),
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/* E0 : SATAXPCIE0 ==> NC */
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PAD_NC(GPP_E0, NONE),
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/* E3 : PROC_GP0 ==> SAR1_INT_L */
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PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE),
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/* E7 : PROC_GP1 ==> NC */
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PAD_NC(GPP_E7, NONE),
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/* E10 : THC0_SPI1_CS# ==> NC */
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PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
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/* E17 : THC0_SPI1_INT# ==> NC */
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PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
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/* E22 : DDPA_CTRLCLK ==> NC */
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PAD_NC(GPP_E22, NONE),
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/* E23 : DDPA_CTRLDATA ==> NC */
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PAD_NC(GPP_E23, NONE),
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/* F6 : CNV_PA_BLANKING ==> NC */
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PAD_NC(GPP_F6, NONE),
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/* F21 : EXT_PWR_GATE2# ==> NC */
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PAD_NC(GPP_F21, NONE),
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/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG),
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/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
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PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG),
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/* H8 : I2C4_SDA ==> NC */
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PAD_NC(GPP_H8, NONE),
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/* H9 : I2C4_SCL ==> NC */
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PAD_NC(GPP_H9, NONE),
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/* H12 : I2C7_SDA ==> NC */
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PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
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/* H13 : I2C7_SCL ==> NC */
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PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
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/* H19 : SRCCLKREQ4# ==> NC */
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PAD_NC(GPP_H19, NONE),
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/* H20 : IMGCLKOUT1 ==> NC */
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PAD_NC(GPP_H20, NONE),
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/* H21 : IMGCLKOUT2 ==> NC */
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PAD_NC(GPP_H21, NONE),
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/* H22 : IMGCLKOUT3 ==> NC */
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PAD_NC(GPP_H22, NONE),
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/* H23 : SRCCLKREQ5# ==> NC */
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PAD_NC(GPP_H23, NONE),
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/* R4 : HDA_RST# ==> DMIC_CLK0_R */
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PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
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/* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
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PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
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/* R6 : I2S2_TXD ==> DMIC_CLK1_R */
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PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
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/* R7 : I2S2_RXD ==> DMIC_DATA1_R */
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PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
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/* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */
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PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
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/* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */
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PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
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/* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */
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PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
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/* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */
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PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
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/* GPD11: LANPHYC ==> NC */
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PAD_NC(GPD11, NONE),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 0, DEEP),
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/*
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* D1 : ISH_GP1 ==> FP_RST_ODL
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* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
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* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
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* early on in bootblock, followed by enabling of power. Reset signal is deasserted
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* later on in ramstage. Since reset signal is asserted in bootblock, it results in
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* FPMCU not working after a S3 resume. This is a known issue.
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*/
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PAD_CFG_GPO(GPP_D1, 0, DEEP),
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/* D2 : ISH_GP2 ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_D2, 1, DEEP),
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/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_D11, 1, DEEP),
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/* E0 : SATAXPCIE0 ==> NC */
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PAD_NC(GPP_E0, NONE),
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/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_E13, NONE, DEEP),
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/* E15 : RSVD_TP ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F18, NONE, DEEP),
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/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* CPU PCIe VGPIO for PEG60 */
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
|
||||
};
|
||||
|
||||
static const struct pad_config romstage_gpio_table[] = {
|
||||
/* B4 : PROC_GP3 ==> SSD_PERST_L */
|
||||
PAD_CFG_GPO(GPP_B4, 1, DEEP),
|
||||
|
||||
/* D1 : ISH_GP1 ==> FP_RST_ODL */
|
||||
PAD_CFG_GPO(GPP_D1, 0, DEEP),
|
||||
/* D2 : ISH_GP2 ==> EN_FP_PWR */
|
||||
PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_override_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(override_gpio_table);
|
||||
return override_gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_romstage_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(romstage_gpio_table);
|
||||
return romstage_gpio_table;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __VARIANT_EC_H__
|
||||
#define __VARIANT_EC_H__
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
/* Enable EC backed Keyboard Backlight in ACPI */
|
||||
#define EC_ENABLE_KEYBOARD_BACKLIGHT
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/zydron/memory src/mainboard/google/brya/variants/zydron/memory/mem_parts_used.txt
|
||||
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL
|
||||
SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/zydron/memory src/mainboard/google/brya/variants/zydron/memory/mem_parts_used.txt
|
||||
|
||||
DRAM Part Name ID to assign
|
||||
MT53E512M32D1NP-046 WT:B 0 (0000)
|
||||
MT53E1G32D2NP-046 WT:B 1 (0001)
|
||||
H54G46CYRBX267 0 (0000)
|
||||
H54G56CYRBX247 1 (0001)
|
||||
K4U6E3S4AB-MGCL 0 (0000)
|
||||
K4UBE3D4AB-MGCL 1 (0001)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
MT53E512M32D1NP-046 WT:B
|
||||
MT53E1G32D2NP-046 WT:B
|
||||
H54G46CYRBX267
|
||||
H54G56CYRBX247
|
||||
K4U6E3S4AB-MGCL
|
||||
K4UBE3D4AB-MGCL
|
||||
|
|
@ -0,0 +1,509 @@
|
|||
fw_config
|
||||
field KB_BL 0 0
|
||||
option KB_BL_ABSENT 0
|
||||
option KB_BL_PRESENT 1
|
||||
end
|
||||
field AUDIO 1 3
|
||||
option AUDIO_UNKNOWN 0
|
||||
option MAX98373_NAU88L25B_I2S 1
|
||||
end
|
||||
field UFC 4 5
|
||||
option UFC_USB 0
|
||||
option UFC_MIPI_OVTI2740 1
|
||||
end
|
||||
field STYLUS 6
|
||||
option STYLUS_ABSENT 0
|
||||
option STYLUS_PRESENT 1
|
||||
end
|
||||
end
|
||||
chip soc/intel/alderlake
|
||||
register "sagv" = "SaGv_Enabled"
|
||||
|
||||
# As per Intel Advisory doc#723158, the change is required to prevent possible
|
||||
# display flickering issue.
|
||||
register "usb2_phy_sus_pg_disable" = "1"
|
||||
|
||||
# GPE configuration
|
||||
register "pmc_gpe0_dw1" = "GPP_D"
|
||||
|
||||
# Acoustic settings
|
||||
register "acoustic_noise_mitigation" = "1"
|
||||
register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
|
||||
register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
|
||||
register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
|
||||
register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
|
||||
|
||||
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
|
||||
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN
|
||||
|
||||
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN
|
||||
|
||||
# FIVR configurations for zydron are disabled since the board doesn't have V1p05 and Vnn
|
||||
# bypass rails implemented.
|
||||
register "ext_fivr_settings" = "{
|
||||
.configure_ext_fivr = 1,
|
||||
}"
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| GSPI1 | Fingerprint MCU |
|
||||
#| I2C0 | Audio |
|
||||
#| I2C1 | cr50 TPM. Early init is |
|
||||
#| | required to set up a BAR |
|
||||
#| | for TPM communication |
|
||||
#| I2C2 | SAR0 |
|
||||
#| I2C3 | Touchscreen |
|
||||
#| I2C5 | Trackpad |
|
||||
#+-------------------+---------------------------+
|
||||
|
||||
register "common_soc_config" = "{
|
||||
.i2c[1] = {
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 600,
|
||||
.fall_time_ns = 400,
|
||||
.data_hold_time_ns = 50,
|
||||
},
|
||||
.i2c[3] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 650,
|
||||
.fall_time_ns = 400,
|
||||
.data_hold_time_ns = 50,
|
||||
},
|
||||
}"
|
||||
|
||||
register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
|
||||
.tdp_pl1_override = 20,
|
||||
.tdp_pl2_override = 43,
|
||||
.tdp_pl4 = 105,
|
||||
}"
|
||||
|
||||
register "power_limits_config[ADL_P_682_28W_CORE]" = "{
|
||||
.tdp_pl1_override = 20,
|
||||
.tdp_pl2_override = 43,
|
||||
.tdp_pl4 = 105,
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device ref dtt on
|
||||
chip drivers/intel/dptf
|
||||
## sensor information
|
||||
register "options.tsr[0].desc" = ""DRAM""
|
||||
register "options.tsr[1].desc" = ""Soc""
|
||||
register "options.tsr[2].desc" = ""Charger""
|
||||
|
||||
# TODO: below values are initial reference values only
|
||||
## Active Policy
|
||||
register "policies.active" = "{
|
||||
[0] = {
|
||||
.target = DPTF_CPU,
|
||||
.thresholds = {
|
||||
TEMP_PCT(85, 90),
|
||||
TEMP_PCT(75, 80),
|
||||
TEMP_PCT(68, 70),
|
||||
TEMP_PCT(62, 60),
|
||||
TEMP_PCT(55, 50),
|
||||
TEMP_PCT(50, 40),
|
||||
TEMP_PCT(40, 30),
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.target = DPTF_TEMP_SENSOR_1,
|
||||
.thresholds = {
|
||||
TEMP_PCT(60, 90),
|
||||
TEMP_PCT(55, 80),
|
||||
TEMP_PCT(52, 70),
|
||||
TEMP_PCT(48, 60),
|
||||
TEMP_PCT(44, 50),
|
||||
TEMP_PCT(40, 40),
|
||||
TEMP_PCT(36, 30),
|
||||
}
|
||||
}
|
||||
}"
|
||||
|
||||
## Passive Policy
|
||||
register "policies.passive" = "{
|
||||
[0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
|
||||
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000),
|
||||
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000),
|
||||
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000),
|
||||
}"
|
||||
|
||||
## Critical Policy
|
||||
register "policies.critical" = "{
|
||||
[0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
|
||||
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
|
||||
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
|
||||
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
|
||||
}"
|
||||
|
||||
register "controls.power_limits" = "{
|
||||
.pl1 = {
|
||||
.min_power = 18000,
|
||||
.max_power = 20000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 200,
|
||||
},
|
||||
.pl2 = {
|
||||
.min_power = 43000,
|
||||
.max_power = 43000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 1000,
|
||||
}
|
||||
}"
|
||||
|
||||
## Charger Performance Control (Control, mA)
|
||||
register "controls.charger_perf" = "{
|
||||
[0] = { 255, 1700 },
|
||||
[1] = { 24, 1500 },
|
||||
[2] = { 16, 1000 },
|
||||
[3] = { 8, 500 }
|
||||
}"
|
||||
|
||||
## Fan Performance Control (Percent, Speed, Noise, Power)
|
||||
register "controls.fan_perf" = "{
|
||||
[0] = { 90, 6700, 220, 2200, },
|
||||
[1] = { 80, 5800, 180, 1800, },
|
||||
[2] = { 70, 5000, 145, 1450, },
|
||||
[3] = { 60, 4900, 115, 1150, },
|
||||
[4] = { 50, 3838, 90, 900, },
|
||||
[5] = { 40, 2904, 55, 550, },
|
||||
[6] = { 30, 2337, 30, 300, },
|
||||
[7] = { 20, 1608, 15, 150, },
|
||||
[8] = { 10, 800, 10, 100, },
|
||||
[9] = { 0, 0, 0, 50, }
|
||||
}"
|
||||
|
||||
## Fan options
|
||||
register "options.fan.fine_grained_control" = "1"
|
||||
register "options.fan.step_size" = "2"
|
||||
|
||||
device generic 0 alias dptf_policy on end
|
||||
end
|
||||
end
|
||||
device ref ipu on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "0x50000"
|
||||
register "acpi_name" = ""IPU0""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
|
||||
|
||||
register "cio2_num_ports" = "1"
|
||||
register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used
|
||||
register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0""
|
||||
register "cio2_prt[0]" = "1"
|
||||
device generic 0 on
|
||||
probe UFC UFC_MIPI_OVTI2740
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref pcie4_0 on
|
||||
# Enable CPU PCIE RP 1 using CLK 0
|
||||
register "cpu_pcie_rp[CPU_RP(1)]" = "{
|
||||
.clk_req = 0,
|
||||
.clk_src = 0,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref tcss_dma0 on
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
|
||||
use tcss_usb3_port1 as dfp[0].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref tcss_dma1 on
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
|
||||
use tcss_usb3_port3 as dfp[0].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c0 on
|
||||
chip drivers/i2c/nau8825
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
|
||||
register "jkdet_enable" = "1"
|
||||
register "jkdet_pull_enable" = "0"
|
||||
register "jkdet_pull_up" = "0"
|
||||
register "jkdet_polarity" = "1" # ActiveLow
|
||||
register "vref_impedance" = "2" # 125kOhm
|
||||
register "micbias_voltage" = "6" # 2.754
|
||||
register "sar_threshold_num" = "4"
|
||||
register "sar_threshold[0]" = "0x0C"
|
||||
register "sar_threshold[1]" = "0x1C"
|
||||
register "sar_threshold[2]" = "0x38"
|
||||
register "sar_threshold[3]" = "0x60"
|
||||
register "sar_hysteresis" = "1"
|
||||
register "sar_voltage" = "6"
|
||||
register "sar_compare_time" = "0" # 500ns
|
||||
register "sar_sampling_time" = "0" # 2us
|
||||
register "short_key_debounce" = "2" # 100ms
|
||||
register "jack_insert_debounce" = "7" # 512ms
|
||||
register "jack_eject_debounce" = "7" # 512ms
|
||||
device i2c 1a on
|
||||
probe AUDIO MAX98373_NAU88L25B_I2S
|
||||
end
|
||||
end
|
||||
chip drivers/i2c/max98373
|
||||
register "vmon_slot_no" = "0"
|
||||
register "imon_slot_no" = "1"
|
||||
register "uid" = "0"
|
||||
register "desc" = ""Right Speaker Amp""
|
||||
register "name" = ""MAXR""
|
||||
device i2c 31 on
|
||||
probe AUDIO MAX98373_NAU88L25B_I2S
|
||||
end
|
||||
end
|
||||
chip drivers/i2c/max98373
|
||||
register "vmon_slot_no" = "2"
|
||||
register "imon_slot_no" = "3"
|
||||
register "uid" = "1"
|
||||
register "desc" = ""Left Speaker Amp""
|
||||
register "name" = ""MAXL""
|
||||
device i2c 32 on
|
||||
probe AUDIO MAX98373_NAU88L25B_I2S
|
||||
end
|
||||
end
|
||||
end #I2C0
|
||||
device ref i2c1 on
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end
|
||||
device ref i2c2 on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = ""INT3474""
|
||||
register "acpi_uid" = "0"
|
||||
register "acpi_name" = ""CAM0""
|
||||
register "chip_name" = ""Ov 2740 Camera""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
|
||||
register "has_power_resource" = "1"
|
||||
|
||||
register "ssdb.lanes_used" = "2"
|
||||
register "ssdb.link_used" = "1"
|
||||
register "num_freq_entries" = "1"
|
||||
register "link_freq[0]" = "360 * MHz"
|
||||
register "remote_name" = ""IPU0""
|
||||
register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
|
||||
|
||||
#Controls
|
||||
register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
|
||||
register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
|
||||
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_F20" #reset
|
||||
register "gpio_panel.gpio[1].gpio_num" = "GPP_C4" #power
|
||||
|
||||
#_ON
|
||||
register "on_seq.ops_cnt" = "4"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
|
||||
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
|
||||
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)"
|
||||
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
|
||||
|
||||
#_OFF
|
||||
register "off_seq.ops_cnt" = "3"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
|
||||
|
||||
device i2c 36 on
|
||||
probe UFC UFC_MIPI_OVTI2740
|
||||
end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
|
||||
register "acpi_uid" = "1"
|
||||
register "acpi_name" = ""NVM0""
|
||||
register "chip_name" = ""AT24 EEPROM""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_NVM"
|
||||
|
||||
register "nvm_size" = "0x2000"
|
||||
register "nvm_pagesize" = "1"
|
||||
register "nvm_readonly" = "1"
|
||||
register "nvm_width" = "0x10"
|
||||
register "nvm_compat" = ""atmel,24c64""
|
||||
|
||||
device i2c 50 on
|
||||
probe UFC UFC_MIPI_OVTI2740
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref i2c3 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN90FC""
|
||||
register "generic.desc" = ""ELAN Touchscreen""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "generic.reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
|
||||
register "generic.reset_delay_ms" = "20"
|
||||
register "generic.reset_off_delay_ms" = "1"
|
||||
register "generic.enable_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
|
||||
register "generic.enable_delay_ms" = "6"
|
||||
register "generic.enable_off_delay_ms" = "30"
|
||||
register "generic.stop_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
|
||||
register "generic.stop_off_delay_ms" = "1"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "generic.disable_gpio_export_in_crs" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 0x10 on end
|
||||
end
|
||||
chip drivers/generic/gpio_keys
|
||||
register "name" = ""PENH""
|
||||
# GPP_D6 is the IRQ source, and GPP_D17 is the wake source
|
||||
register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D6)"
|
||||
register "key.wake_gpe" = "GPE0_DW1_17"
|
||||
register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
|
||||
register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
|
||||
register "key.dev_name" = ""EJCT""
|
||||
register "key.linux_code" = "SW_PEN_INSERTED"
|
||||
register "key.linux_input_type" = "EV_SW"
|
||||
register "key.label" = ""pen_eject""
|
||||
device generic 0 on
|
||||
probe STYLUS STYLUS_PRESENT
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref i2c5 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||
register "wake" = "GPE0_DW2_14"
|
||||
register "detect" = "1"
|
||||
device i2c 15 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""PNP0C50""
|
||||
register "generic.desc" = ""Synaptics Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||
register "generic.wake" = "GPE0_DW2_14"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 0x2c on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp6 off end # PCIE6 WWAN
|
||||
device ref pcie_rp8 off end # PCIE8 SD card
|
||||
device ref pcie_rp9 off end # PCIE9-12 SSD
|
||||
device ref gspi1 on
|
||||
chip drivers/spi/acpi
|
||||
register "name" = ""CRFP""
|
||||
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||
register "uid" = "1"
|
||||
register "compat_string" = ""google,cros-ec-spi""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
|
||||
register "wake" = "GPE0_DW2_15"
|
||||
register "has_power_resource" = "1"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
|
||||
register "enable_delay_ms" = "3"
|
||||
device spi 0 on end
|
||||
end # FPMCU
|
||||
end
|
||||
device ref pch_espi on
|
||||
chip ec/google/chromeec
|
||||
use conn0 as mux_conn[0]
|
||||
use conn1 as mux_conn[1]
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device ref pmc hidden
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port1 as usb2_port
|
||||
use tcss_usb3_port1 as usb3_port
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port3 as usb2_port
|
||||
use tcss_usb3_port3 as usb3_port
|
||||
device generic 1 alias conn1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C1 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref tcss_usb3_port3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C1 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Camera""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port6 on
|
||||
probe UFC UFC_USB
|
||||
end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A0 (MLB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
|
||||
device ref usb2_port9 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A0 (MLB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <device/pci_ids.h>
|
||||
|
||||
const struct cpu_power_limits limits[] = {
|
||||
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
|
||||
{ PCI_DID_INTEL_ADL_P_ID_7, 15, 12000, 15000, 40000, 40000, 105000 },
|
||||
{ PCI_DID_INTEL_ADL_P_ID_6, 15, 12000, 15000, 40000, 40000, 105000 },
|
||||
{ PCI_DID_INTEL_ADL_P_ID_5, 28, 18000, 20000, 43000, 43000, 105000 },
|
||||
{ PCI_DID_INTEL_ADL_P_ID_3, 28, 18000, 20000, 43000, 43000, 105000 },
|
||||
};
|
||||
|
||||
void variant_devtree_update(void)
|
||||
{
|
||||
size_t total_entries = ARRAY_SIZE(limits);
|
||||
variant_update_power_limits(limits, total_entries);
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <chip.h>
|
||||
#include <fw_config.h>
|
||||
#include <baseboard/variants.h>
|
||||
|
||||
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
|
||||
{
|
||||
config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
|
||||
MAX98373_NAU88L25B_I2S));
|
||||
}
|
||||
Loading…
Reference in New Issue