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sb/intel/common: Add a common interface to set final OPs settings 

This adds a common place to set the final opprefix, optype and opmenu,
with a hook to override the opmenu.

Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2019-05-28 13:06:34 +02:00 committed by Martin Roth
parent 3fcea0dfad
commit 92185e373e
2 changed files with 79 additions and 0 deletions
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41
src/southbridge/intel/common/spi.c
View File

@ -31,6 +31,8 @@
#include <spi-generic.h>
#include "spi.h"
#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
@ -1048,6 +1050,45 @@ static int spi_flash_protect(const struct spi_flash *flash,
return 0;
}
void spi_finalize_ops(void)
{
struct ich_spi_controller *cntlr = &g_cntlr;
u16 spi_opprefix;
u16 optype = 0;
struct intel_swseq_spi_config spi_config = {
{0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */
{ /* OPTYPE and OPCODE */
{0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */
{0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */
{0x03, READ_WITH_ADDR}, /* READ: Read Data */
{0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */
{0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */
{0x9f, READ_NO_ADDR}, /* RDID: Read ID */
{0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */
{0x0b, READ_WITH_ADDR}, /* FAST: Fast Read */
}
};
int i;
if (spi_locked())
return;
intel_southbridge_override_spi(&spi_config);
spi_opprefix = spi_config.opprefixes[0]
| (spi_config.opprefixes[1] << 8);
writew_(spi_opprefix, cntlr->preop);
for (i = 0; i < ARRAY_SIZE(spi_config.ops); i++) {
optype |= (spi_config.ops[i].type & 3) << (i * 2);
writeb_(spi_config.ops[i].op, &cntlr->opmenu[i]);
}
writew_(optype, &cntlr->optype);
}
__weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config)
{
}
static const struct spi_ctrlr spi_ctrlr = {
.xfer_vector = xfer_vectors,
.max_xfer_size = member_size(struct ich9_spi_regs, fdata),

38
src/southbridge/intel/common/spi.h Normal file
View File

@ -0,0 +1,38 @@
/*
* This file is part of the coreboot project.
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOUTHBRIDGE_INTEL_SPI_H
#define SOUTHBRIDGE_INTEL_SPI_H
enum optype {
READ_NO_ADDR = 0,
WRITE_NO_ADDR = 1,
READ_WITH_ADDR = 2,
WRITE_WITH_ADDR = 3
};
struct intel_spi_op {
u8 op;
enum optype type;
};
struct intel_swseq_spi_config {
u8 opprefixes[2];
struct intel_spi_op ops[8];
};
void spi_finalize_ops(void);
void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config);
#endif