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nb/intel/sandybridge/raminit_mrc.c: Use <device/dram/ddr3.h> macros 

Change-Id: Icca870d1c97a2737dec3f31b0f2e4c3222c711ae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS 2022-01-26 08:01:08 +01:00 committed by Felix Held
parent a233eb4b0a
commit 921b99ed4b
1 changed files with 13 additions and 12 deletions
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25
src/northbridge/intel/sandybridge/raminit_mrc.c
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@ -5,6 +5,7 @@
#include <cf9_reset.h>
#include <string.h>
#include <device/device.h>
#include <device/dram/ddr3.h>
#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cbmem.h>
@ -422,14 +423,14 @@ void setup_sdram_meminfo(struct pei_data *pei_data)
dimm->dimm_num = 0;
dimm->bank_locator = i * 2;
memcpy(dimm->serial, /* bytes 122-125 */
&pei_data->spd_data[0][122],
sizeof(uint8_t) * 4);
&pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM],
sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN);
memcpy(dimm->module_part_number, /* bytes 128-145 */
&pei_data->spd_data[0][128],
sizeof(uint8_t) * 18);
&pei_data->spd_data[0][SPD_DIMM_PART_NUM],
sizeof(uint8_t) * SPD_DIMM_PART_LEN);
dimm->mod_id = /* bytes 117/118 */
(pei_data->spd_data[0][118] << 8) |
(pei_data->spd_data[0][117] & 0xFF);
(pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
(pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
dimm->mod_type = DDR3_SPD_SODIMM;
dimm->bus_width = MEMORY_BUS_WIDTH_64;
dimm_cnt++;
@ -446,14 +447,14 @@ void setup_sdram_meminfo(struct pei_data *pei_data)
dimm->dimm_num = 1;
dimm->bank_locator = i * 2;
memcpy(dimm->serial, /* bytes 122-125 */
&pei_data->spd_data[0][122],
sizeof(uint8_t) * 4);
&pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM],
sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN);
memcpy(dimm->module_part_number, /* bytes 128-145 */
&pei_data->spd_data[0][128],
sizeof(uint8_t) * 18);
&pei_data->spd_data[0][SPD_DIMM_PART_NUM],
sizeof(uint8_t) * SPD_DIMM_PART_LEN);
dimm->mod_id = /* bytes 117/118 */
(pei_data->spd_data[0][118] << 8) |
(pei_data->spd_data[0][117] & 0xFF);
(pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
(pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
dimm->mod_type = DDR3_SPD_SODIMM;
dimm->bus_width = MEMORY_BUS_WIDTH_64;
dimm_cnt++;