GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/tigerlake: Remove scs.asl 

Remove EMMC and SD card ACPI devices copied from Ice Lake.
Tiger Lake does not support these controllers.

BUG=b:151208782
TEST= Build volteer board

Change-Id: I4b3e37f93b94757d16d775fb27bee644d9dc539e
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40228
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra 2020-04-06 13:35:18 +05:30 committed by Subrata Banik
parent 9a90a439a2
commit 9225fd5040
1 changed files with 0 additions and 122 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

122
src/soc/intel/tigerlake/acpi/scs.asl
View File

@ -1,122 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#include <soc/pcr_ids.h>
Scope (\_SB.PCI0) {
/*
* Clear register 0x1C20/0x4820
* Arg0 - PCR Port ID
*/
Method(SCSC, 1, Serialized)
{
PCRA (Arg0, 0x1C20, 0x0)
PCRA (Arg0, 0x4820, 0x0)
}
/* EMMC */
Device(PEMC) {
Name(_ADR, 0x001A0000)
Name (_DDN, "eMMC Controller")
Name (TEMP, 0)
OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
Field(SCSR, WordAcc, NoLock, Preserve) {
Offset (0x84), /* PMECTRLSTATUS */
PMCR, 16,
Offset (0xA2), /* PG_CONFIG */
, 2,
PGEN, 1, /* PG_ENABLE */
}
Method(_INI) {
/* Clear register 0x1C20/0x4820 */
SCSC (PID_EMMC)
}
Method(_PS0, 0, Serialized) {
Stall (50) // Sleep 50 us
Store(0, PGEN) // Disable PG
/* Clear register 0x1C20/0x4820 */
SCSC (PID_EMMC)
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
Store (PMCR, TEMP)
}
Method(_PS3, 0, Serialized) {
Store(1, PGEN) // Enable PG
/* Set Power State to D3 */
Or (PMCR, 0x0003, PMCR)
Store (PMCR, TEMP)
}
Device (CARD)
{
Name (_ADR, 0x00000008)
Method (_RMV, 0, NotSerialized)
{
Return (0)
}
}
}
/* SD CARD */
Device (SDXC)
{
Name (_ADR, 0x00140005)
Name (_DDN, "SD Controller")
Name (TEMP, 0)
OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
Field (SDPC, WordAcc, NoLock, Preserve)
{
Offset (0x84), /* PMECTRLSTATUS */
PMCR, 16,
Offset (0xA2), /* PG_CONFIG */
, 2,
PGEN, 1, /* PG_ENABLE */
}
Method(_INI)
{
/* Clear register 0x1C20/0x4820 */
SCSC (PID_SDX)
}
Method (_PS0, 0, Serialized)
{
Store (0, PGEN) /* Disable PG */
/* Clear register 0x1C20/0x4820 */
SCSC (PID_SDX)
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
Store (PMCR, TEMP)
}
Method (_PS3, 0, Serialized)
{
Store (1, PGEN) /* Enable PG */
/* Set Power State to D3 */
Or (PMCR, 0x0003, PMCR)
Store (PMCR, TEMP)
}
Device (CARD)
{
Name (_ADR, 0x00000008)
Method (_RMV, 0, NotSerialized)
{
Return (1)
}
}
} /* Device (SDXC) */
}