mb/google/poppy/variants: Set VmxEnable to 1

This change sets VmxEnable to 1 to match the kernel setting. 
If this feature is enabled at the kernel level and not in FSP, 
then there is an issue where FSP expects it to be disabled so 
it forces a cold reboot on every warm reboot.

BUG=b:78129261
BRANCH=poppy

Change-Id: Idedbde1d8eb0c9e959733b7b50e5dec804d61cae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25698
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2018-04-16 23:26:55 -07:00
parent 7fb2ab6d43
commit 92263853ad
4 changed files with 4 additions and 0 deletions

View File

@ -59,6 +59,7 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"

View File

@ -58,6 +58,7 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"

View File

@ -59,6 +59,7 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"

View File

@ -59,6 +59,7 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"