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SPI: Add Fast Read to the OPMENU for locked down SPI 

The chips we are using do not use BE52 (block erase 0x52)
so we can use that opcode menu location to enable fast read.

Change-Id: I18f3e0e5e462b052358654faa0c82103b23a9f61
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Duncan Laurie 2012-10-08 14:30:06 -07:00 committed by Stefan Reinauer
parent fb8632ab58
commit 924342bb2b
1 changed files with 2 additions and 2 deletions
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4
src/southbridge/intel/bd82x6x/pch.h
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@ -524,8 +524,8 @@ int smbus_read_byte(unsigned device, unsigned address);
#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
#define SPI_OPTYPE_6 0x03 /* Write, address required */ #define SPI_OPTYPE_6 0x03 /* Write, address required */
#define SPI_OPMENU_7 0x52 /* BE52: Block Erase 0x52 */ #define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
#define SPI_OPTYPE_7 0x03 /* Write, address required */ #define SPI_OPTYPE_7 0x02 /* Read, address required */
#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
(SPI_OPMENU_5 << 8) | SPI_OPMENU_4) (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)