google/clapper: fix up devicetree
When clapper was upstreamed, the devicetree was pulled from the wrong firmware branch, leading to some incorrect settings and touchpad, touchscreen, and audio not working. Correct devicetree settings using Chromium branch firmware-clapper-5216.199.B Test: build/boot google/clapper, verify touchpad/touchscreen/audio functional under Linux (GalliumOS 3.0/kernel 4.16.18). Change-Id: Iacfce575a054b1f484149f36d0aa83d20d034d8a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -32,16 +32,25 @@ chip soc/intel/baytrail
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register "sdcard_cap_high" = "0x0"
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# Enable devices in ACPI mode
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register "lpe_acpi_mode" = "1"
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register "lpss_acpi_mode" = "1"
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register "scc_acpi_mode" = "1"
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# Enable PIPEA as DP_C
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register "gpu_pipea_port_select" = "2" # DP_C
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register "gpu_pipea_power_cycle_delay" = "5" # 400ms
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register "gpu_pipea_power_on_delay" = "2000" # 200ms
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register "gpu_pipea_light_on_delay" = "10" # 1ms
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register "gpu_pipea_power_cycle_delay" = "6" # 600ms
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register "gpu_pipea_power_on_delay" = "5000" # 500ms
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register "gpu_pipea_light_on_delay" = "70" # 7ms
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register "gpu_pipea_power_off_delay" = "500" # 50ms
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register "gpu_pipea_light_off_delay" = "2000" # 200ms
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# VR PS2 control
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register "vnn_ps2_enable" = "1"
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register "vcc_ps2_enable" = "1"
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# Disable SLP_X stretching after SUS power well fail.
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register "disable_slp_x_stretch_sus_fail" = "1"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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@ -59,11 +68,11 @@ chip soc/intel/baytrail
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device pci 18.2 on end # I2C2
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device pci 18.3 off end # I2C3
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device pci 18.4 off end # I2C4
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device pci 18.5 off end # I2C5
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device pci 18.5 on end # I2C5
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device pci 18.6 on end # I2C6
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device pci 18.7 off end # I2C7
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device pci 1a.0 off end # TXE
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device pci 1b.0 off end # HDA
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device pci 1b.0 on end # HDA
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device pci 1c.0 on end # PCIE_PORT1
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device pci 1c.1 on end # PCIE_PORT2
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device pci 1c.2 off end # PCIE_PORT3
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