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mb/gigabyte/ga-g41m-es2l: Remove PMBASE settings and commented code. 

Fixed incorrect comment regarding port 80 LPC route.

Change-Id: Ifbb73753d5a0737418b869085f2329a02504e5dc
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13466
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
This commit is contained in:
Damien Zammit 2016-01-26 17:24:48 +11:00 committed by Martin Roth
parent c70966cd26
commit 9253ce60c4
1 changed files with 2 additions and 17 deletions
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19
src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
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@ -58,21 +58,6 @@ static void mb_gpio_init(void)
outl(0x000000f0, DEFAULT_GPIOBASE + 0x34);
outl(0x00000083, DEFAULT_GPIOBASE + 0x38);
/* Set default power management registers */
pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1);
outw(0x0011, DEFAULT_PMBASE + 0x00);
outw(0x0120, DEFAULT_PMBASE + 0x02);
outl(0x00001c01, DEFAULT_PMBASE + 0x04);
outl(0x00bb29d2, DEFAULT_PMBASE + 0x08);
outl(0x000000a0, DEFAULT_PMBASE + 0x10);
outl(0xc5000000, DEFAULT_PMBASE + 0x28);
outl(0x00000040, DEFAULT_PMBASE + 0x2c);
outw(0x13e0, DEFAULT_PMBASE + 0x44);
outw(0x003f, DEFAULT_PMBASE + 0x60);
outw(0x0800, DEFAULT_PMBASE + 0x68);
outw(0x0008, DEFAULT_PMBASE + 0x6a);
outw(0x003f, DEFAULT_PMBASE + 0x72);
/* Set default GPIOs on superio */
ite_reg_write(GPIO_DEV, 0x25, 0x00);
ite_reg_write(GPIO_DEV, 0x26, 0xc7);
@ -137,8 +122,8 @@ void main(unsigned long bist)
// ch0 ch1
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
/* Disable watchdog timer and route port 80 to LPC */
RCBA32(0x3410) = (RCBA32(0x3410) | 0x20);// & ~0x4;
/* Disable watchdog timer */
RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
/* Set southbridge and Super I/O GPIOs. */
mb_gpio_init();