* cleanup ricoh rl5c476 code:
- drop duplicate udelay function - simplify code flow - some cosmetics on comments Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
733263c44c
commit
925b6c0c43
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@ -5,7 +5,6 @@ extern struct chip_operations southbridge_ricoh_rl5c476_ops;
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struct southbridge_ricoh_rl5c476_config {
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int enable_cf;
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};
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#endif /* _SOUTHBRIDGE_RL5C476 */
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#endif /* _SOUTHBRIDGE_RICOH_RL5C476 */
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2004 Nick Barker <nick.barker9@btinternet.com>
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* (C) Copyright 2004-2005 Nick Barker <nick.barker@btinternet.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -16,8 +16,6 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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/* (C) Copyright 2005 Nick Barker <nick.barker@btinternet.com
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brought into line with the current architecture of coreboot */
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#include <arch/io.h>
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#include <device/device.h>
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@ -32,21 +30,13 @@
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static int enable_cf_boot = 0;
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static unsigned int cf_base;
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static void udelay(int i)
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{
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for(; i > 0 ; i--)
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inb(0x80);
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}
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static void rl5c476_init(device_t dev)
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{
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//unsigned char enables;
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pc16reg_t *pc16;
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unsigned char *base;
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/* cardbus controller function 1 for CF Socket */
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printk_debug("rl5c476 init\n");
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printk_debug("Ricoh RL5c476: Initializing.\n");
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printk_debug("CF Base = %0x\n",cf_base);
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@ -54,98 +44,120 @@ static void rl5c476_init(device_t dev)
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pci_write_config16(dev,0x82,0x00a0);
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/* set up second slot as compact flash port if asked to do so */
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if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
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/* make sure isa interrupts are enabled */
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pci_write_config16(dev,0x3e,0x0780);
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/* pick up where 16 bit card control structure is (0x800 bytes into config structure) */
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base = (unsigned char *)pci_read_config32(dev,0x10);
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pc16 = (pc16reg_t *)(base + 0x800);
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/* disable memory and io windows and turn off socket power */
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pc16->pwctrl = 0;
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/* disable irq lines */
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pc16->igctrl = 0;
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/* disable memory and I/O windows */
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pc16->awinen = 0;
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/* reset card, configure for I/O and set IRQ line */
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pc16->igctrl = 0x69;
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// set io window 0 for 1e0 - 1ef
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/* note this now sets CF up on a contiguous I/O window of 16 bytes, 0x1e0 to 0x1ef
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Be warned that this is not a standard IDE address as automatically detected by the likes
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of Filo, and would need patching to recognise these addresses as an IDE drive */
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/* an earlier version of this driver set up 2 io windows to emulate the expected addresses
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for IDE2, however the pcmcia package within Linux then could not re-initiailse the
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device as it tried to take control of it. So I belive it is easier to patch Filo or the like
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to pick up this drive rather than playing silly games as the kernel tries to boot.
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*/
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pc16->iostl0 = 0xe0;
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pc16->iosth0 = 1;
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pc16->iospl0 = 0xef;
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pc16->iosph0 = 1;
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pc16->ioffl0 = 0;
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pc16->ioffh0 = 0;
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// clear window 1
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pc16->iostl1 = 0;
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pc16->iosth1 = 0;
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pc16->iospl1 = 0;
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pc16->iosph1 = 0;
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pc16->ioffl1 = 0x0;
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pc16->ioffh1 = 0;
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// set up CF config window
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pc16->smpga0 = cf_base>>24;
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pc16->smsth0 = (cf_base>>20)&0x0f;
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pc16->smstl0 = (cf_base>>12)&0xff;
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pc16->smsph0 = ((cf_base>>20)&0x0f) | 0x80;
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pc16->smspl0 = (cf_base>>12)&0xff;
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pc16->moffl0 = 0;
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pc16->moffh0 = 0x40;
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// set I/O width for Auto Data width
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pc16->ioctrl = 0x22;
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// enable I/O window 0 and 1
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pc16->awinen = 0xc1;
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pc16->miscc1 = 1;
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// apply power and enable outputs
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pc16->pwctrl = 0xb0;
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if (!enable_cf_boot) {
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printk_debug("CF boot not enabled.\n");
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return;
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}
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// delay could be optimised, but this works
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udelay(100000);
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pc16->igctrl = 0x69;
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// 16 bit CF always have first config byte at 0x200 into Config structure,
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// but CF+ May Not according to spec - should locate through reading tuple data,
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// but this will do for now !!!
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unsigned char *cptr;
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cptr = (unsigned char *)(cf_base + 0x200);
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printk_debug("CF Config = %x\n",*cptr);
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// set CF to decode 16 IO bytes on any 16 byte boundary - rely on the io
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// windows of the bridge set up above to map those bytes into the
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// addresses for ide controller 3 (0x1e8 - 0x1ef and 0x3ed - 0x3ee)
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*cptr = 0x41;
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if (PCI_FUNC(dev->path.pci.devfn) != 1) {
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// Only configure if second CF slot.
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return;
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}
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/* make sure isa interrupts are enabled */
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pci_write_config16(dev,0x3e,0x0780);
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/* pick up where 16 bit card control structure is
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* (0x800 bytes into config structure)
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*/
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base = (unsigned char *)pci_read_config32(dev,0x10);
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pc16 = (pc16reg_t *)(base + 0x800);
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/* disable memory and io windows and turn off socket power */
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pc16->pwctrl = 0;
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/* disable irq lines */
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pc16->igctrl = 0;
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/* disable memory and I/O windows */
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pc16->awinen = 0;
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/* reset card, configure for I/O and set IRQ line */
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pc16->igctrl = 0x69;
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/* set io window 0 for 1e0 - 1ef */
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/* NOTE: This now sets CF up on a contiguous I/O window of
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* 16 bytes, 0x1e0 to 0x1ef.
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* Be warned that this is not a standard IDE address as
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* automatically detected by the likes of FILO, and would need
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* patching to recognise these addresses as an IDE drive.
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*
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* An earlier version of this driver set up 2 I/O windows to
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* emulate the expected addresses for IDE2, however the PCMCIA
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* package within Linux then could not re-initialize the
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* device as it tried to take control of it. So I believe it is
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* easier to patch Filo or the like to pick up this drive
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* rather than playing silly games as the kernel tries to
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* boot.
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*
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* Nonetheless, FILO needs a special option enabled to boot
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* from this configuration, and it needs to clean up
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* afterwards. Please refer to FILO documentation and source
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* code for more details.
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*/
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pc16->iostl0 = 0xe0;
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pc16->iosth0 = 1;
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pc16->iospl0 = 0xef;
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pc16->iosph0 = 1;
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pc16->ioffl0 = 0;
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pc16->ioffh0 = 0;
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/* clear window 1 */
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pc16->iostl1 = 0;
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pc16->iosth1 = 0;
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pc16->iospl1 = 0;
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pc16->iosph1 = 0;
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pc16->ioffl1 = 0x0;
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pc16->ioffh1 = 0;
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/* set up CF config window */
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pc16->smpga0 = cf_base>>24;
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pc16->smsth0 = (cf_base>>20)&0x0f;
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pc16->smstl0 = (cf_base>>12)&0xff;
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pc16->smsph0 = ((cf_base>>20)&0x0f) | 0x80;
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pc16->smspl0 = (cf_base>>12)&0xff;
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pc16->moffl0 = 0;
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pc16->moffh0 = 0x40;
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/* set I/O width for Auto Data width */
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pc16->ioctrl = 0x22;
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/* enable I/O window 0 and 1 */
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pc16->awinen = 0xc1;
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pc16->miscc1 = 1;
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/* apply power and enable outputs */
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pc16->pwctrl = 0xb0;
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// delay could be optimised, but this works
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udelay(100000);
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pc16->igctrl = 0x69;
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/* 16 bit CF always have first config byte at 0x200 into
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* Config structure, but CF+ may not according to spec -
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* should locate through reading tuple data, but this should
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* do for now.
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*/
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unsigned char *cptr;
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cptr = (unsigned char *)(cf_base + 0x200);
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printk_debug("CF Config = %x\n",*cptr);
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/* Set CF to decode 16 IO bytes on any 16 byte boundary -
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* rely on the io windows of the bridge set up above to
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* map those bytes into the addresses for IDE controller 3
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* (0x1e8 - 0x1ef and 0x3ed - 0x3ee)
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*/
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*cptr = 0x41;
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}
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void rl5c476_read_resources(device_t dev)
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@ -153,9 +165,12 @@ void rl5c476_read_resources(device_t dev)
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struct resource *resource;
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/* for cf socket we need an extra memory window for the control structure of the cf itself */
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/* For CF socket we need an extra memory window for
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* the control structure of the CF itself
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*/
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if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
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resource = new_resource(dev,1); /* fake index as it isn't in pci config space */
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/* fake index as it isn't in PCI config space */
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resource = new_resource(dev, 1);
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resource->flags |= IORESOURCE_MEM ;
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resource->size = 0x1000;
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resource->align = resource->gran = 12;
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@ -1,7 +1,6 @@
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/*
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* (C) Copyright 2004 Nick Barker <nick.barker9@btinternet.com>
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*
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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