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mb/amd/majolica:Set IRQ for GPIO controller 

AMD GPIO driver will not load if IRQ is not set. As a consequence,
it does not clear the interrupt when waking from S0i3.

BUG=178728116
TEST=Perform 2 S0i3 cycles, confirming second cycle does not return
instantly due to first interrupt not being cleared.

Change-Id: I3072263e8e68f939a47ed4125444c60133087824
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Jason Glenesk 2021-04-26 16:34:04 -07:00 committed by Felix Held
parent 7a0b9b680b
commit 925e3896d0
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/amd/majolica/mainboard.c
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@ -52,7 +52,7 @@ static const struct fch_irq_routing {
{ PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, { PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
{ PIRQ_SATA, PIRQ_NC, PIRQ_NC }, { PIRQ_SATA, PIRQ_NC, PIRQ_NC },
{ PIRQ_EMMC, PIRQ_NC, PIRQ_NC }, { PIRQ_EMMC, PIRQ_NC, PIRQ_NC },
{ PIRQ_GPIO, PIRQ_NC, PIRQ_NC }, { PIRQ_GPIO, 7, 7 },
{ PIRQ_I2C2, PIRQ_NC, PIRQ_NC }, { PIRQ_I2C2, PIRQ_NC, PIRQ_NC },
{ PIRQ_I2C3, PIRQ_NC, PIRQ_NC }, { PIRQ_I2C3, PIRQ_NC, PIRQ_NC },
{ PIRQ_UART0, 4, 4 }, { PIRQ_UART0, 4, 4 },