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ep405pc board 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson 2003-07-23 22:20:55 +00:00
parent 5bed979a9b
commit 92624c10d1
2 changed files with 105 additions and 0 deletions
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19
src/mainboard/embeddedplanet/ep405pc/Config.lb Normal file
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##
## Config file for the Motorola Sandpoint III development system.
## Note that this has only been tested with the Altimus 7410 PMC.
##
arch ppc end
cpu ppc4xx end
##
## Include the secondary Configuration files
##
southbridge winbond/w83c553 end
##
## Build the objects we have code for in this directory.
##
addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a"
makedefine CFLAGS += -g

86
targets/embeddedplanet/ep405pc/Config.lb Normal file
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# Config file for Embedded Planet EP405PC board
# This will make a target directory of ./ep405pc
loadoptions
target ep405pc
uses ARCH CROSS_COMPILE
uses HAVE_OPTION_TABLE
uses CONFIG_SANDPOINT_ALTIMUS
uses CONFIG_COMPRESS
uses NO_POST
uses CONFIG_IDE_STREAM
uses IDE_BOOT_DRIVE
uses USE_ELF_BOOT
uses IDE_SWAB IDE_OFFSET
uses ROM_SIZE ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses _ROMBASE
uses CACHE_RAM_BASE
uses CACHE_RAM_SIZE
uses STACK_SIZE HEAP_SIZE
uses MAINBOARD
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
## use a cross compiler
option CROSS_COMPILE="powerpc-eabi-"
## Use chip configuration
option CONFIG_CHIP_CONFIGURE=1
## We don't use compressed image
option CONFIG_COMPRESS=0
## Turn off POST codes
option NO_POST=1
## Boot linux from IDE
option CONFIG_IDE_STREAM=1
option IDE_BOOT_DRIVE=0
option USE_ELF_BOOT=1
option IDE_SWAB=1
option IDE_OFFSET=0
option ROM_SIZE=1048576
## LinuxBIOS C code runs at this location in RAM
option _RAMBASE=0x00100000
## For the trick of using cache as ram
## put the fake ram location at this address
option CACHE_RAM_BASE=0x00200000
option CACHE_RAM_SIZE=0x00004000
##
## Use a 64K stack
##
option STACK_SIZE=0x10000
##
## Use a 64K heap
##
option HEAP_SIZE=0x10000
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
option ROM_SECTION_SIZE=ROM_SIZE
option ROM_SECTION_OFFSET=0
##
## Compute where this copy of linuxBIOS will start in the boot rom
##
option _ROMBASE=0xfff00000
romimage "normal"
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
option ROM_IMAGE_SIZE=49152
option CONFIG_SANDPOINT_ALTIMUS=1
mainboard embeddedplanet/ep405pc
end
buildrom ROM_SIZE "normal"