diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index 3f1358a2f8..e3e5735c3b 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -94,8 +94,6 @@ _cache_as_ram_setup:
 
 #endif
 
-	call early_all_cores
-
 	/* Must maintain 16-byte stack alignment here. */
 	pushl	$0x0
 	pushl	$0x0
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
index 72aac3eedd..0ecfeb2bb6 100644
--- a/src/drivers/amd/agesa/romstage.c
+++ b/src/drivers/amd/agesa/romstage.c
@@ -27,15 +27,6 @@
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
-#if !CONFIG(POSTCAR_STAGE)
-#error "Only POSTCAR_STAGE is supported."
-#endif
-
-void asmlinkage early_all_cores(void)
-{
-	amd_initmmio();
-}
-
 void __weak platform_once(struct sysinfo *cb)
 {
 	board_BeforeAgesa(cb);
@@ -57,6 +48,9 @@ void *asmlinkage romstage_main(unsigned long bist)
 	u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24);
 	int cbmem_initted = 0;
 
+	/* Enable PCI MMIO configuration. */
+	amd_initmmio();
+
 	fill_sysinfo(cb);
 
 	if ((initial_apic_id == 0) && boot_cpu()) {
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h
index 59f5bb91aa..46f7e1d5c9 100644
--- a/src/include/cpu/amd/car.h
+++ b/src/include/cpu/amd/car.h
@@ -5,8 +5,6 @@
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
-void asmlinkage early_all_cores(void);
-
 void *asmlinkage romstage_main(unsigned long bist);
 
 #endif