From 926be7736115125ec1706befed6e4cde16e98aef Mon Sep 17 00:00:00 2001
From: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Date: Wed, 25 Oct 2023 18:11:58 +0800
Subject: [PATCH] mb/google/nissa/var/joxer: Override tdp pl1 value for DTT
 tuning

Follow thermal validation, override tdp pl1 in 6w ADL_N platform to
10w and override tdp pl1 in 15w ADL_N platform to 20w.

BUG=b:307365403
TEST=USE="project_joxer emerge-nissa coreboot"

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I8dd743e65b9e5fbd6aa2fd9c1b87c7bd487c8174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78650
Reviewed-by: ChiaLing <chia-ling.hou@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
---
 .../brya/variants/joxer/overridetree.cb       | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/src/mainboard/google/brya/variants/joxer/overridetree.cb b/src/mainboard/google/brya/variants/joxer/overridetree.cb
index 135041d0a7..187afe5d64 100644
--- a/src/mainboard/google/brya/variants/joxer/overridetree.cb
+++ b/src/mainboard/google/brya/variants/joxer/overridetree.cb
@@ -136,6 +136,25 @@ chip soc/intel/alderlake
 		},
 	}"
 
+	# Power limit config
+
+	register "power_limits_config[ADL_N_081_15W_CORE]" = "{
+		.tdp_pl1_override = 20,
+		.tdp_pl2_override = 35,
+		.tdp_pl4 = 83,
+	}"
+	register "power_limits_config[ADL_N_041_6W_CORE]" = "{
+		.tdp_pl1_override = 10,
+		.tdp_pl2_override = 25,
+		.tdp_pl4 = 78,
+	}"
+
+	register "power_limits_config[ADL_N_021_6W_CORE]" = "{
+		.tdp_pl1_override = 10,
+		.tdp_pl2_override = 25,
+		.tdp_pl4 = 78,
+	}"
+
 	device domain 0 on
 		device ref dtt on
 			chip drivers/intel/dptf