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nb/intel/sandybridge: Drop invalid `DEFAULT_RCBABASE` macro 

RCBA is located in the PCH. Replace all instances with the
already-defined `DEFAULT_RCBA` macro, which is equivalent.

Change-Id: I4b92737820b126d32da09b69e09675464aa22e31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45348
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-09-14 16:22:22 +02:00
parent 10240510a7
commit 92717ff3e4
15 changed files with 14 additions and 15 deletions
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2
src/mainboard/asus/p8z77-m_pro/early_init.c
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@ -93,7 +93,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,

2
src/mainboard/google/butterfly/early_init.c
View File

@ -87,7 +87,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,

2
src/mainboard/google/link/early_init.c
View File

@ -94,7 +94,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,

2
src/mainboard/google/parrot/early_init.c
View File

@ -62,7 +62,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,

2
src/mainboard/google/stout/early_init.c
View File

@ -99,7 +99,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,

2
src/mainboard/intel/dcp847ske/romstage.c
View File

@ -22,7 +22,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,

2
src/mainboard/intel/emeraldlake2/early_init.c
View File

@ -59,7 +59,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,

2
src/mainboard/kontron/ktqm77/early_init.c
View File

@ -64,7 +64,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,

2
src/mainboard/lenovo/x220/early_init.c
View File

@ -20,7 +20,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,

2
src/mainboard/roda/rv11/variants/rv11/early_init.c
View File

@ -18,7 +18,7 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data)
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,

2
src/mainboard/roda/rv11/variants/rw11/early_init.c
View File

@ -48,7 +48,7 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data)
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,

2
src/mainboard/samsung/lumpy/early_init.c
View File

@ -125,7 +125,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,

2
src/mainboard/samsung/stumpy/early_init.c
View File

@ -109,7 +109,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,

2
src/northbridge/intel/sandybridge/raminit_mrc.c
View File

@ -253,7 +253,7 @@ static void southbridge_fill_pei_data(struct pei_data *pei_data)
pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE;
pei_data->wdbbar = 0x04000000;
pei_data->wdbsize = 0x1000;
pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE;
pei_data->rcba = (uintptr_t)DEFAULT_RCBA;
pei_data->pmbase = DEFAULT_PMBASE;
pei_data->gpiobase = DEFAULT_GPIOBASE;
pei_data->gbe_enable = dev && dev->enabled;

1
src/northbridge/intel/sandybridge/sandybridge.h
View File

@ -29,7 +29,6 @@
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
#endif
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#define DEFAULT_RCBABASE ((u8 *)0xfed1c000)
#define GFXVT_BASE 0xfed90000ULL
#define VTVC0_BASE 0xfed91000ULL