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mb/*/*/buildOpts.c: Drop BLDCFG_IR_PIN_CONTROL 

This does not exist anywhere in the entire coreboot tree. Drop it.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: I80320a20f4b44896e72d701a1d98786cb3a93dcc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
This commit is contained in:
Angel Pons 2020-05-20 23:19:17 +02:00 committed by Nico Huber
parent 477b4f8886
commit 927f6ae84a
14 changed files with 0 additions and 14 deletions
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1
src/mainboard/amd/olivehill/buildOpts.c
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@ -306,7 +306,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL olivehill_gpio[] = {
{183, Function1, GpioIn | GpioOutEnB | PullUpB},

1
src/mainboard/amd/parmer/buildOpts.c
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@ -307,7 +307,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL parmer_gpio[] = {
{183, Function1, GpioIn | GpioOutEnB | PullUpB},

1
src/mainboard/amd/thatcher/buildOpts.c
View File

@ -307,7 +307,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
#define FCH_NO_XHCI_SUPPORT TRUE
GPIO_CONTROL thatcher_gpio[] = {
{183, Function1, PullUpB},

1
src/mainboard/asrock/imb-a180/buildOpts.c
View File

@ -306,7 +306,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL imba180_gpio[] = {
{183, Function1, GpioIn | GpioOutEnB | PullUpB},

1
src/mainboard/asus/am1i-a/buildOpts.c
View File

@ -318,7 +318,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL imba180_gpio[] = {
{183, Function1, GpioIn | GpioOutEnB | PullUpB},

1
src/mainboard/asus/f2a85-m/buildOpts.c
View File

@ -309,7 +309,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
//#define FCH_NO_XHCI_SUPPORT FALSE
GPIO_CONTROL f2a85_m_gpio[] = {
// {183, Function1, PullUpB},

1
src/mainboard/bap/ode_e20XX/buildOpts.c
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@ -305,7 +305,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL gizmo2_gpio[] = {
{183, Function1, GpioIn | GpioOutEnB | PullUpB},

1
src/mainboard/biostar/a68n_5200/buildOpts.c
View File

@ -306,7 +306,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL olivehill_gpio[] = {
{183, Function1, GpioIn | GpioOutEnB | PullUpB},

1
src/mainboard/biostar/am1ml/buildOpts.c
View File

@ -306,7 +306,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL imba180_gpio[] = {
{183, Function1, GpioIn | GpioOutEnB | PullUpB},

1
src/mainboard/gizmosphere/gizmo2/buildOpts.c
View File

@ -305,7 +305,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL gizmo2_gpio[] = {
{183, Function1, GpioIn | GpioOutEnB | PullUpB},

1
src/mainboard/hp/abm/buildOpts.c
View File

@ -310,7 +310,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL hp_abm_gpio[] = {
{ 45, Function2, GpioOutEnB | Sticky }, // Signal input APU_SD_LED

1
src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
View File

@ -309,7 +309,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
/*
* The GPIO control is not well documented in AGESA, but is in the BKDG

1
src/mainboard/lenovo/g505s/buildOpts.c
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@ -309,7 +309,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
/*
* The GPIO control is not well documented in AGESA, but is in the BKDG

1
src/mainboard/msi/ms7721/buildOpts.c
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@ -309,7 +309,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
//#define FCH_NO_XHCI_SUPPORT FALSE
GPIO_CONTROL ms7721_m_gpio[] = {
// {183, Function1, PullUpB},