soc/mediatek: Adjust hsa, hbp, hfp packets for MIPI_DSI_MODE_LINE_END
ANX7625 requires the line packets to end at the same time. Otherwise, the display will be shifted. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Jacuzzi Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I5949de1a9a1947fa188233787166a478b1de68b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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@ -224,6 +224,13 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
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"the panel may not work properly.\n");
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"the panel may not work properly.\n");
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}
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}
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if (mode_flags & MIPI_DSI_MODE_LINE_END) {
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hsync_active_byte = DIV_ROUND_UP(hsync_active_byte, lanes) * lanes - 2;
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hbp_byte = DIV_ROUND_UP(hbp_byte, lanes) * lanes - 2;
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hfp_byte = DIV_ROUND_UP(hfp_byte, lanes) * lanes - 2;
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hbp_byte -= (edid->mode.ha * bytes_per_pixel + 2) % lanes;
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}
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if (hfp_byte + hbp_byte < MIN_HFP_BYTE + MIN_HBP_BYTE) {
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if (hfp_byte + hbp_byte < MIN_HFP_BYTE + MIN_HBP_BYTE) {
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printk(BIOS_ERR, "Calculated hfp_byte and hbp_byte are too small, "
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printk(BIOS_ERR, "Calculated hfp_byte and hbp_byte are too small, "
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"the panel may not work properly.\n");
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"the panel may not work properly.\n");
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@ -39,7 +39,9 @@ enum {
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/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
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/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
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MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10),
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MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10),
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/* transmit data in low power */
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/* transmit data in low power */
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MIPI_DSI_MODE_LPM = BIT(11)
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MIPI_DSI_MODE_LPM = BIT(11),
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/* dsi per line's data end same time on all lanes */
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MIPI_DSI_MODE_LINE_END = BIT(12),
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};
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};
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struct dsi_regs {
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struct dsi_regs {
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