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soc/mediatek: Adjust hsa, hbp, hfp packets for MIPI_DSI_MODE_LINE_END 

ANX7625 requires the line packets to end at the same time.
Otherwise, the display will be shifted.

BUG=b:173603645
BRANCH=kukui
TEST=Display is normal on Jacuzzi

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I5949de1a9a1947fa188233787166a478b1de68b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Jitao Shi 2021-02-01 13:21:45 +08:00 committed by Hung-Te Lin
parent 7de5677643
commit 927fa6d04c
2 changed files with 10 additions and 1 deletions
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7
src/soc/mediatek/common/dsi.c
View File

@ -224,6 +224,13 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
"the panel may not work properly.\n");
}
if (mode_flags & MIPI_DSI_MODE_LINE_END) {
hsync_active_byte = DIV_ROUND_UP(hsync_active_byte, lanes) * lanes - 2;
hbp_byte = DIV_ROUND_UP(hbp_byte, lanes) * lanes - 2;
hfp_byte = DIV_ROUND_UP(hfp_byte, lanes) * lanes - 2;
hbp_byte -= (edid->mode.ha * bytes_per_pixel + 2) % lanes;
}
if (hfp_byte + hbp_byte < MIN_HFP_BYTE + MIN_HBP_BYTE) {
printk(BIOS_ERR, "Calculated hfp_byte and hbp_byte are too small, "
"the panel may not work properly.\n");

4
src/soc/mediatek/common/include/soc/dsi_common.h
View File

@ -39,7 +39,9 @@ enum {
/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10),
/* transmit data in low power */
MIPI_DSI_MODE_LPM = BIT(11)
MIPI_DSI_MODE_LPM = BIT(11),
/* dsi per line's data end same time on all lanes */
MIPI_DSI_MODE_LINE_END = BIT(12),
};
struct dsi_regs {