From 928a9c8f048874018ab14a0c66108c22b7b04da2 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 24 Feb 2022 00:51:11 +0100 Subject: [PATCH] cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic number Signed-off-by: Felix Held Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308 Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/cpu/amd/agesa/family14/fixme.c | 3 ++- src/cpu/amd/agesa/family15tn/fixme.c | 3 ++- src/cpu/amd/agesa/family16kb/fixme.c | 3 ++- src/cpu/amd/pi/00730F01/fixme.c | 3 ++- src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl | 6 ++++-- src/northbridge/intel/ironlake/northbridge.c | 3 ++- src/northbridge/intel/pineview/northbridge.c | 3 ++- src/soc/intel/xeon_sp/acpi/southcluster.asl | 3 ++- 8 files changed, 18 insertions(+), 9 deletions(-) diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index b47c4f0f65..16caf40f15 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -28,7 +29,7 @@ void amd_initcpuio(void) PciData |= 1 << 7; // set NP (non-posted) bit LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 + PciData = (HPET_BASE_ADDRESS >> 8) | 3; // lowest NP address is HPET at FED00000 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Map the remaining PCI hole as posted MMIO */ diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index ebfa07da08..feb85bfe43 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -28,7 +29,7 @@ void amd_initcpuio(void) PciData |= 1 << 7; /* set NP (non-posted) bit */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Map the remaining PCI hole as posted MMIO */ diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c index 3771a064c7..5e43b17d3b 100644 --- a/src/cpu/amd/agesa/family16kb/fixme.c +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -28,7 +29,7 @@ void amd_initcpuio(void) PciData |= 1 << 7; /* set NP (non-posted) bit */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Map the remaining PCI hole as posted MMIO */ diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 9b208ecc4c..689fdecd15 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -32,7 +33,7 @@ void amd_initcpuio(void) LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); /* lowest NP address is HPET at FED00000 */ - PciData = (0xFED00000 >> 8) | 3; + PciData = (HPET_BASE_ADDRESS >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Map the remaining PCI hole as posted MMIO */ diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl b/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl index da670cf889..e9b48584ac 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + /**************************************************************** * HPET ****************************************************************/ @@ -8,7 +10,7 @@ Scope(\_SB) { Device(HPET) { Name(_HID, EISAID("PNP0103")) Name(_UID, 0) - OperationRegion(HPTM, SystemMemory, 0xFED00000, 0x400) + OperationRegion(HPTM, SystemMemory, HPET_BASE_ADDRESS, 0x400) Field(HPTM, DWordAcc, Lock, Preserve) { VEND, 32, PRD, 32, @@ -27,7 +29,7 @@ Scope(\_SB) { } Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadOnly, - 0xFED00000, // Address Base + HPET_BASE_ADDRESS, // Address Base 0x00000400, // Address Length ) }) diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index b5ad824623..2137e3b419 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -48,7 +49,7 @@ static void add_fixed_resources(struct device *dev, int index) 0xff800000-0xffffffff ROM. */ resource = new_resource(dev, index++); - resource->base = (resource_t) 0xfed00000; + resource->base = (resource_t) HPET_BASE_ADDRESS; resource->size = (resource_t) 0x00100000; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 80b46117c5..9e272235d2 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -26,7 +27,7 @@ static void add_fixed_resources(struct device *dev, int index) struct resource *resource; resource = new_resource(dev, index++); - resource->base = (resource_t) 0xfed00000; + resource->base = (resource_t) HPET_BASE_ADDRESS; resource->size = (resource_t) 0x00100000; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE diff --git a/src/soc/intel/xeon_sp/acpi/southcluster.asl b/src/soc/intel/xeon_sp/acpi/southcluster.asl index d1fd98fbab..eb687784e7 100644 --- a/src/soc/intel/xeon_sp/acpi/southcluster.asl +++ b/src/soc/intel/xeon_sp/acpi/southcluster.asl @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include Name(_HID,EISAID("PNP0A08")) // PCIe @@ -120,7 +121,7 @@ Name (MCRS, ResourceTemplate() { DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0xfed00000, 0xfedfffff, 0x00000000, + 0x00000000, HPET_BASE_ADDRESS, 0xfedfffff, 0x00000000, 0x00100000,,, PCHR) QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,