mainboard/asrock: add ASRock B75 Pro3-M
Tested: - i5-3550 and DIMM configurations: 2+0+2+2, 0+2+2+2, 2+2+2+2, 4+2+4+2 - debug output from serial port, EHCI debug port not found - Arch Linux (Linux 4.11.5) loaded from SeaBIOS, GRUB2, and Linux payload - all PCI and PCI Express slots Issues: - sometimes the machine fails to boot, with serial debug output it can be seen it stucks after SMM initialization, and more likely to fail to boot when serial cable is attached - no S3 resume (not tested in vendor firmware) Change-Id: I94fbfcee06921538b32aa3c23efa642e7e405ef6 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/20227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Iru Cai
Martin Roth
parent
b016f144cc
commit
928c6c6336
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@ -0,0 +1,60 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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if BOARD_ASROCK_B75PRO3_M
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select BOARD_ROMSIZE_KB_8192
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select CPU_INTEL_SOCKET_RPGA989
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select SUPERIO_NUVOTON_NCT6776
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_INT15
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_C216
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select USE_NATIVE_RAMINIT
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select MAINBOARD_HAS_LIBGFXINIT
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config HAVE_IFD_BIN
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bool
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default n
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config HAVE_ME_BIN
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bool
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default n
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config MAINBOARD_DIR
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string
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default asrock/b75pro3-m
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config MAINBOARD_PART_NUMBER
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string
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default "B75 Pro3-M"
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x1e49
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x1849
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config MAX_CPUS
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int
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default 8
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endif
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@ -0,0 +1,2 @@
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config BOARD_ASROCK_B75PRO3_M
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bool "B75 Pro3-M"
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@ -0,0 +1,18 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@ -0,0 +1,48 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Device (P0P1)
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{
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Name (_ADR, 0x001E0000)
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Method (_PRT, 0)
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{
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If (PICM) {
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Return (Package () {
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Package () {0x0001FFFF, 0, 0, 0x14},
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Package () {0x0001FFFF, 1, 0, 0x15},
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Package () {0x0001FFFF, 2, 0, 0x16},
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Package () {0x0001FFFF, 3, 0, 0x17},
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Package () {0x0002FFFF, 0, 0, 0x17},
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Package () {0x0002FFFF, 1, 0, 0x14},
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Package () {0x0002FFFF, 2, 0, 0x15},
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Package () {0x0002FFFF, 3, 0, 0x16}
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})
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} Else {
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Return (Package () {
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Package () {0x0001FFFF, 0, \_SB.PCI0.LPCB.LNKE, 0},
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Package () {0x0001FFFF, 1, \_SB.PCI0.LPCB.LNKF, 0},
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Package () {0x0001FFFF, 2, \_SB.PCI0.LPCB.LNKG, 0},
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Package () {0x0001FFFF, 3, \_SB.PCI0.LPCB.LNKH, 0},
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Package () {0x0002FFFF, 0, \_SB.PCI0.LPCB.LNKH, 0},
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Package () {0x0002FFFF, 1, \_SB.PCI0.LPCB.LNKE, 0},
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Package () {0x0002FFFF, 2, \_SB.PCI0.LPCB.LNKF, 0},
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Package () {0x0002FFFF, 3, \_SB.PCI0.LPCB.LNKG, 0}
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})
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}
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}
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}
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@ -0,0 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Method(_WAK,1)
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{
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Return(Package(){0,0})
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}
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Method(_PTS,1)
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{
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}
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@ -0,0 +1,35 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/bd82x6x/nvs.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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/* Disable USB ports in S3 by default */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/* Disable USB ports in S5 by default */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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// the lid is open by default.
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gnvs->lids = 1;
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gnvs->tcrt = 100;
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gnvs->tpsv = 90;
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}
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Category: desktop
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Board URL: http://www.asrock.com/mb/Intel/B75%20Pro3-M/
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ROM protocol: SPI
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Flashrom support: n
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ROM package: DIP-8
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ROM socketed: y
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Release year: 2012
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@ -0,0 +1,180 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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chip northbridge/intel/sandybridge
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
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register "gfx.link_frequency_270_mhz" = "0"
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register "gfx.ndid" = "3"
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register "gfx.use_spread_spectrum_clock" = "0"
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register "gpu_cpu_backlight" = "0x00000000"
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register "gpu_dp_b_hotplug" = "4"
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register "gpu_dp_c_hotplug" = "4"
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register "gpu_dp_d_hotplug" = "4"
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register "gpu_panel_port_select" = "0"
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register "gpu_panel_power_backlight_off_delay" = "0"
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register "gpu_panel_power_backlight_on_delay" = "0"
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register "gpu_panel_power_cycle_delay" = "4"
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register "gpu_panel_power_down_delay" = "0"
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register "gpu_panel_power_up_delay" = "0"
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register "gpu_pch_backlight" = "0x00000000"
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device cpu_cluster 0x0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0x0 on
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end
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end
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chip cpu/intel/model_206ax
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register "c1_acpower" = "1"
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register "c1_battery" = "1"
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register "c2_acpower" = "3"
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register "c2_battery" = "3"
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register "c3_acpower" = "5"
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register "c3_battery" = "5"
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device lapic 0xacac off
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end
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end
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end
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device domain 0x0 on
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device pci 00.0 on
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subsystemid 0x1849 0x0150
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end
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device pci 01.0 on
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subsystemid 0x1849 0x0151
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end
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device pci 02.0 on
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subsystemid 0x1849 0x0152
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end
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chip southbridge/intel/bd82x6x
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register "c2_latency" = "0x0065"
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register "docking_supported" = "0"
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register "gen1_dec" = "0x000c0291"
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register "gen2_dec" = "0x000c0241"
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register "gen3_dec" = "0x000c0251"
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register "p_cnt_throttling_supported" = "0"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "0"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x3f"
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register "superspeed_capable_ports" = "0x0000000f"
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register "xhci_overcurrent_mapping" = "0x00000c03"
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register "xhci_switchable_ports" = "0x0000000f"
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register "spi_uvscc" = "0x2005"
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register "spi_lvscc" = "0x2005"
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device pci 14.0 on # USB 3.0 Controller
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subsystemid 0x1849 0x1e31
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end
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device pci 16.0 on # Management Engine Interface 1
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subsystemid 0x1849 0x1e3a
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end
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device pci 16.1 off # Management Engine Interface 2
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end
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device pci 16.2 off # Management Engine IDE-R
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end
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device pci 16.3 on # Management Engine KT
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subsystemid 0x1849 0x1e3d
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end
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device pci 19.0 off # Intel Gigabit Ethernet
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end
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device pci 1a.0 on # USB2 EHCI #2
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subsystemid 0x1849 0x1e2d
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end
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device pci 1b.0 on # High Definition Audio Audio controller
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subsystemid 0x1849 0x8892
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end
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device pci 1c.0 on # PCIe Port #1
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subsystemid 0x1849 0x1e10
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end
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device pci 1c.1 off # PCIe Port #2
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end
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device pci 1c.2 off # PCIe Port #3
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end
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device pci 1c.3 off # PCIe Port #4
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end
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device pci 1c.4 on # PCIe Port #5, ASMedia ASM1062 SATA Controller
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subsystemid 0x1849 0x1e18
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end
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register "pcie_aspm_f4" = "0x80" # Disable ASPM for ASMedia SATA controller
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device pci 1c.5 on # PCIe Port #6, Realtek PCIe GbE Controller
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subsystemid 0x1849 0x1e1a
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end
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device pci 1c.6 off # PCIe Port #7
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end
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device pci 1c.7 off # PCIe Port #8
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end
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device pci 1d.0 on # USB2 EHCI #1
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subsystemid 0x1849 0x1e26
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end
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device pci 1e.0 on # PCI bridge
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subsystemid 0x1849 0x244e
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end
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device pci 1f.0 on # LPC bridge
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subsystemid 0x1849 0x1e49
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chip superio/nuvoton/nct6776
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 on # Parallel port
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# global
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irq 0x1c = 0x80
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irq 0x27 = 0xc0
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irq 0x2a = 0x62
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# parallel port
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io 0x60 = 0x378
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irq 0x70 = 5
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drq 0x74 = 3
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end
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off end # COM2, IR
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 off end # GPIO6-9
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device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA
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device pnp 2e.9 off end # GPIO2-5
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device pnp 2e.a on # ACPI
|
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irq 0xe0 = 0x01
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irq 0xe3 = 0x14
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irq 0xe6 = 0x4c
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irq 0xe9 = 0x02
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irq 0xf0 = 0x20
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end
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device pnp 2e.b off end # HWM, front pannel LED
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device pnp 2e.d on end # VID
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device pnp 2e.e off end # CIR WAKE-UP
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device pnp 2e.f on end # GPIO Push-Pull or Open-drain
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device pnp 2e.14 on end # SVID
|
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device pnp 2e.16 on end # Deep Sleep
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device pnp 2e.17 on end # GPIOA
|
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end
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||||
end
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device pci 1f.2 on # SATA Controller 1
|
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subsystemid 0x1849 0x1e02
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||||
end
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device pci 1f.3 on # SMBus
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subsystemid 0x1849 0x1e22
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||||
end
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device pci 1f.5 off # SATA Controller 2
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||||
end
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device pci 1f.6 off # Thermal
|
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end
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||||
end
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||||
end
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||||
end
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@ -0,0 +1,47 @@
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/*
|
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
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#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
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#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
|
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DefinitionBlock(
|
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"dsdt.aml",
|
||||
"DSDT",
|
||||
0x03, // DSDT revision: ACPI v3.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20141018 // OEM revision
|
||||
)
|
||||
{
|
||||
// Some generic macros
|
||||
#include "acpi/platform.asl"
|
||||
#include <cpu/intel/model_206ax/acpi/cpu.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
|
||||
/* global NVS and variables. */
|
||||
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
|
||||
#include "acpi/pci.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
--
|
||||
-- Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(HDMI1,
|
||||
HDMI2,
|
||||
Analog,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -0,0 +1,190 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
.gpio2 = GPIO_MODE_NATIVE,
|
||||
.gpio3 = GPIO_MODE_NATIVE,
|
||||
.gpio4 = GPIO_MODE_NATIVE,
|
||||
.gpio5 = GPIO_MODE_NATIVE,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio8 = GPIO_MODE_GPIO,
|
||||
.gpio9 = GPIO_MODE_NATIVE,
|
||||
.gpio10 = GPIO_MODE_NATIVE,
|
||||
.gpio11 = GPIO_MODE_NATIVE,
|
||||
.gpio12 = GPIO_MODE_GPIO,
|
||||
.gpio13 = GPIO_MODE_GPIO,
|
||||
.gpio14 = GPIO_MODE_NATIVE,
|
||||
.gpio15 = GPIO_MODE_GPIO,
|
||||
.gpio16 = GPIO_MODE_GPIO,
|
||||
.gpio17 = GPIO_MODE_GPIO,
|
||||
.gpio18 = GPIO_MODE_NATIVE,
|
||||
.gpio19 = GPIO_MODE_NATIVE,
|
||||
.gpio20 = GPIO_MODE_NATIVE,
|
||||
.gpio21 = GPIO_MODE_NATIVE,
|
||||
.gpio22 = GPIO_MODE_NATIVE,
|
||||
.gpio23 = GPIO_MODE_NATIVE,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio25 = GPIO_MODE_NATIVE,
|
||||
.gpio26 = GPIO_MODE_NATIVE,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
.gpio29 = GPIO_MODE_GPIO,
|
||||
.gpio30 = GPIO_MODE_NATIVE,
|
||||
.gpio31 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_INPUT,
|
||||
.gpio1 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
|
||||
.gpio8 = GPIO_DIR_INPUT,
|
||||
.gpio12 = GPIO_DIR_OUTPUT,
|
||||
.gpio13 = GPIO_DIR_INPUT,
|
||||
.gpio15 = GPIO_DIR_OUTPUT,
|
||||
.gpio16 = GPIO_DIR_INPUT,
|
||||
.gpio17 = GPIO_DIR_INPUT,
|
||||
.gpio24 = GPIO_DIR_OUTPUT,
|
||||
.gpio27 = GPIO_DIR_INPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
.gpio29 = GPIO_DIR_OUTPUT,
|
||||
.gpio31 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio12 = GPIO_LEVEL_HIGH,
|
||||
.gpio15 = GPIO_LEVEL_LOW,
|
||||
.gpio24 = GPIO_LEVEL_LOW,
|
||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
.gpio29 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio13 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_NATIVE,
|
||||
.gpio36 = GPIO_MODE_NATIVE,
|
||||
.gpio37 = GPIO_MODE_NATIVE,
|
||||
.gpio38 = GPIO_MODE_NATIVE,
|
||||
.gpio39 = GPIO_MODE_NATIVE,
|
||||
.gpio40 = GPIO_MODE_NATIVE,
|
||||
.gpio41 = GPIO_MODE_NATIVE,
|
||||
.gpio42 = GPIO_MODE_NATIVE,
|
||||
.gpio43 = GPIO_MODE_NATIVE,
|
||||
.gpio44 = GPIO_MODE_NATIVE,
|
||||
.gpio45 = GPIO_MODE_NATIVE,
|
||||
.gpio46 = GPIO_MODE_NATIVE,
|
||||
.gpio47 = GPIO_MODE_NATIVE,
|
||||
.gpio48 = GPIO_MODE_NATIVE,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_NATIVE,
|
||||
.gpio51 = GPIO_MODE_NATIVE,
|
||||
.gpio52 = GPIO_MODE_NATIVE,
|
||||
.gpio53 = GPIO_MODE_NATIVE,
|
||||
.gpio54 = GPIO_MODE_NATIVE,
|
||||
.gpio55 = GPIO_MODE_NATIVE,
|
||||
.gpio56 = GPIO_MODE_NATIVE,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
.gpio58 = GPIO_MODE_NATIVE,
|
||||
.gpio59 = GPIO_MODE_NATIVE,
|
||||
.gpio60 = GPIO_MODE_NATIVE,
|
||||
.gpio61 = GPIO_MODE_NATIVE,
|
||||
.gpio62 = GPIO_MODE_NATIVE,
|
||||
.gpio63 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_OUTPUT,
|
||||
.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio57 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_HIGH,
|
||||
.gpio33 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_NATIVE,
|
||||
.gpio65 = GPIO_MODE_NATIVE,
|
||||
.gpio66 = GPIO_MODE_NATIVE,
|
||||
.gpio67 = GPIO_MODE_NATIVE,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_NATIVE,
|
||||
.gpio71 = GPIO_MODE_NATIVE,
|
||||
.gpio72 = GPIO_MODE_GPIO,
|
||||
.gpio73 = GPIO_MODE_NATIVE,
|
||||
.gpio74 = GPIO_MODE_NATIVE,
|
||||
.gpio75 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio72 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0892, /* Codec Vendor / Device ID: Realtek */
|
||||
0x18498892, /* Subsystem ID */
|
||||
|
||||
0x0000000f, /* Number of 4 dword sets */
|
||||
/* NID 0x01: Subsystem ID. */
|
||||
AZALIA_SUBVENDOR(0x0, 0x18498892),
|
||||
|
||||
/* NID 0x11. */
|
||||
AZALIA_PIN_CFG(0x0, 0x11, 0x411111f0),
|
||||
|
||||
/* NID 0x12. */
|
||||
AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),
|
||||
|
||||
/* NID 0x14. */
|
||||
AZALIA_PIN_CFG(0x0, 0x14, 0x01014010),
|
||||
|
||||
/* NID 0x15. */
|
||||
AZALIA_PIN_CFG(0x0, 0x15, 0x01011012),
|
||||
|
||||
/* NID 0x16. */
|
||||
AZALIA_PIN_CFG(0x0, 0x16, 0x01016011),
|
||||
|
||||
/* NID 0x17. */
|
||||
AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
|
||||
|
||||
/* NID 0x18. */
|
||||
AZALIA_PIN_CFG(0x0, 0x18, 0x01a19840),
|
||||
|
||||
/* NID 0x19. */
|
||||
AZALIA_PIN_CFG(0x0, 0x19, 0x02a19950),
|
||||
|
||||
/* NID 0x1a. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1a, 0x0181304f),
|
||||
|
||||
/* NID 0x1b. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1b, 0x02214120),
|
||||
|
||||
/* NID 0x1c. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),
|
||||
|
||||
/* NID 0x1d. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1d, 0x4005e601),
|
||||
|
||||
/* NID 0x1e. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1e, 0x01452130),
|
||||
|
||||
/* NID 0x1f. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0),
|
||||
0x80862806, /* Codec Vendor / Device ID: Intel */
|
||||
0x80860101, /* Subsystem ID */
|
||||
|
||||
0x00000004, /* Number of 4 dword sets */
|
||||
/* NID 0x01: Subsystem ID. */
|
||||
AZALIA_SUBVENDOR(0x3, 0x80860101),
|
||||
|
||||
/* NID 0x05. */
|
||||
AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
|
||||
|
||||
/* NID 0x06. */
|
||||
AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
|
||||
|
||||
/* NID 0x07. */
|
||||
AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include <drivers/intel/gma/int15.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
|
||||
GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
GMA_INT15_BOOT_DISPLAY_CRT, 0);
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "northbridge/intel/sandybridge/raminit_native.h"
|
||||
#include <superio/nuvoton/nct6776/nct6776.h>
|
||||
#include <superio/nuvoton/common/nuvoton.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
|
||||
|
||||
void pch_enable_lpc(void)
|
||||
{
|
||||
pci_write_config16(PCH_LPC_DEV, LPC_EN,
|
||||
CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
|
||||
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0000);
|
||||
}
|
||||
|
||||
void rcba_config(void)
|
||||
{
|
||||
RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
|
||||
}
|
||||
|
||||
const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
{ 1, 0, 0 },
|
||||
{ 1, 0, 0 },
|
||||
{ 1, 1, 1 },
|
||||
{ 1, 1, 1 },
|
||||
{ 1, 1, 2 },
|
||||
{ 1, 1, 2 },
|
||||
{ 1, 0, 3 },
|
||||
{ 1, 0, 3 },
|
||||
{ 1, 0, 4 },
|
||||
{ 1, 0, 4 },
|
||||
{ 1, 0, 6 },
|
||||
{ 1, 1, 5 },
|
||||
{ 1, 1, 5 },
|
||||
{ 1, 0, 6 },
|
||||
};
|
||||
|
||||
void mainboard_early_init(int s3resume)
|
||||
{
|
||||
}
|
||||
|
||||
void mainboard_config_superio(void)
|
||||
{
|
||||
/* Set GPIOs on superio, enable UART */
|
||||
nuvoton_pnp_enter_conf_state(SERIAL_DEV);
|
||||
pnp_set_logical_device(SERIAL_DEV);
|
||||
|
||||
pnp_write_config(SERIAL_DEV, 0x1c, 0x80);
|
||||
pnp_write_config(SERIAL_DEV, 0x27, 0x80);
|
||||
pnp_write_config(SERIAL_DEV, 0x2a, 0x60);
|
||||
|
||||
nuvoton_pnp_exit_conf_state(SERIAL_DEV);
|
||||
|
||||
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
}
|
||||
|
||||
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
||||
{
|
||||
read_spd(&spd[0], 0x50, id_only);
|
||||
read_spd(&spd[1], 0x51, id_only);
|
||||
read_spd(&spd[2], 0x52, id_only);
|
||||
read_spd(&spd[3], 0x53, id_only);
|
||||
}
|
||||
Loading…
Reference in New Issue