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sb/intel/ibexpeak/early_pch.c: Use PCI_BASE_ADDRESS_0 macro 

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If74e1db623d65d639041d49caf0ca1b6c0e1f2ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes Haouas 2022-02-24 07:22:01 +01:00 committed by Felix Held
parent bd90a226a3
commit 92c2ccda0c
1 changed files with 2 additions and 1 deletions
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src/southbridge/intel/ibexpeak/early_pch.c
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@ -48,7 +48,8 @@ void ibexpeak_setup_bars(void)
outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06); outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06);
printk(BIOS_DEBUG, " done.\n"); printk(BIOS_DEBUG, " done.\n");
pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR); pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_BASE_ADDRESS_0,
(uintptr_t)DEFAULT_HECIBAR);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
} }