From 92d38997906be4b1b7b91e2a4d007b09a24419c1 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Wed, 14 Sep 2022 11:06:06 -0700 Subject: [PATCH] soc/intel/alderlake: Explicitly disable Energy Efficiency Turbo FSP silicon 3347 changed the default value of the EnergyEfficientTurbo Updateable Product Data (UPD), enabling the Energy Efficient Turbo feature by default. This feature prevents the cores from entering Turbo frequency under heavy load. As a result of this FSP change, coreboot explicitly disables this feature to stay consistent with commit `caa5f59279e Revert "soc/intel/alderlake: Enable energy efficiency turbo mode"'. BRANCH=firmware-brya-14505.B BUG=b:246831841 TEST=verify that bit 19 of MSR 0x1fc is set. 'iotools rdmsr 0 0x1fc' Signed-off-by: Jeremy Compostella Change-Id: I7498f87eb4be666b34cfccd0449a2b67a92eb9db Reviewed-on: https://review.coreboot.org/c/coreboot/+/67650 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Nick Vaccaro --- src/soc/intel/alderlake/fsp_params.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 31277fb5ac..016d8ad3ab 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -948,6 +948,9 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, s_cfg->PsOnEnable = 1; s_cfg->PkgCStateLimit = LIMIT_AUTO; + /* Disable Energy Efficient Turbo mode */ + s_cfg->EnergyEfficientTurbo = 0; + /* VccIn Aux Imon IccMax. Values are in 1/4 Amp increments and range is 0-512. */ s_cfg->VccInAuxImonIccImax = get_vccin_aux_imon_iccmax() * 4 / MILLIAMPS_TO_AMPS;