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mb/google/rex: Enable DPTF functionality for Rex 

Enable DPTF functionality for Meteor Lake Rex board.

BUG=b:262498724
TEST=Booted to OS and verified DPTF entries in ACPI SSDT on Rex board.

Change-Id: I87b2d71650be9ce940d9452bf4a76d4cd1ddba52
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70884
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
zhaojohn 2022-12-16 09:27:19 -08:00 committed by Martin L Roth
parent 387ec919d9
commit 92d49da163
3 changed files with 10 additions and 0 deletions
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2
src/mainboard/google/rex/Kconfig
View File

@ -4,6 +4,8 @@ config BOARD_GOOGLE_REX_COMMON
select DRIVERS_GENERIC_MAX98357A select DRIVERS_GENERIC_MAX98357A
select DRIVERS_I2C_GENERIC select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID select DRIVERS_I2C_HID
select DRIVERS_INTEL_DPTF
select DRIVERS_INTEL_DPTF_SUPPORTS_TPCH
select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_INTEL_USB4_RETIMER
select DRIVERS_SOUNDWIRE_ALC5682 select DRIVERS_SOUNDWIRE_ALC5682
select DRIVERS_WIFI_GENERIC select DRIVERS_WIFI_GENERIC

3
src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
View File

@ -14,6 +14,9 @@ chip soc/intel/meteorlake
# S0ix enable # S0ix enable
register "s0ix_enable" = "1" register "s0ix_enable" = "1"
# DPTF enable
register "dptf_enable" = "1"
# Enable CNVi BT # Enable CNVi BT
register "cnvi_bt_core" = "true" register "cnvi_bt_core" = "true"

5
src/mainboard/google/rex/variants/rex0/overridetree.cb
View File

@ -118,6 +118,11 @@ chip soc/intel/meteorlake
}" }"
device domain 0 on device domain 0 on
device ref dtt on
chip drivers/intel/dptf
device generic 0 alias dptf_policy on end
end
end
device ref pcie_rp9 on device ref pcie_rp9 on
# Enable SSD Card PCIE 9 using clk 4 # Enable SSD Card PCIE 9 using clk 4
register "pcie_rp[PCH_RP(9)]" = "{ register "pcie_rp[PCH_RP(9)]" = "{