Documentation/../../icelake: Add Ice Lake coreboot development documentation
Add documentation for Ice Lake processor family coreboot development. Documented so far: * What is Ice Lake * Development Strategy * Create coreboot Image * Flashing coreboot Change-Id: Ief4df6ca11f95b75ecddeb560f7887bfadced086 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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# Intel Ice Lake coreboot development
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## Introduction
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This document captures the coreboot development strategy for Intel SoC named Ice lake.
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The Ice Lake processor family is the next generation Intel® Core processor family.
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These processors are built using Intel's 10 nm+ process.
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* [What is Ice Lake?](https://www.intel.in/content/www/in/en/design/products-and-solutions/processors-and-chipsets/ice-lake/overview.html)
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## Development Strategy
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Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel common code development model".
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1. Intel develops initial Firmware code for Ice Lake SoC.
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2. Additionally provides Firmware code support for Intel Reference Platform (RVP), known as Ice lake RVP with same SoC.
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```eval_rst
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:doc:`../../../mainboard/intel/icelake_rvp.md`
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```
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3. OEMs to design based on reference platform and make use of mainboard sample code. Dragonegg is Ice Lake based mainboard developed by Google
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```eval_rst
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:doc:`../../../mainboard/google/dragonegg.md`
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```
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### Summary:
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* SoC is Ice Lake.
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* Reference platform is icelake_rvp.
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* OEM board is Dragonegg.
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## Create coreboot Image
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1. Clone latest coreboot code as below
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```bash
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$ git clone https://review.coreboot.org/coreboot.git
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```
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2. Place blobs (ucode, me.bin and FSP packages) in appropriate locations
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Note:
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Consider the fact that ucode and ME kit for Ice Lake SoC will be available from Intel VIP site.
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After product launch, FSP binary will be available externally as any other program.
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3. Create coreboot .config
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4. Build toolchain
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```bash
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CPUS=$(nproc--ignore=1) make crossgcc-i386 iasl
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```
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5. Build image
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```bash
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$ make # the image is generated as build/coreboot.rom
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```
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## Flashing coreboot
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Flashing mechanism might be different between Intel RVP (Reference Validation Platform) and Chromebooks:
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* Make use of dediprog while flashing coreboot image on Intel-RVP
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* For Chromebook related platform like dragonegg, one can flash via servo:
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```bash
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$ dut-control spi2_vref:pp3300 spi2_buf_en:on spi2_buf_on_flex_en:on warm_reset:on
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$ sudo flashrom -n -p ft2232_spi:type=servo-v2 -w <bios_image>
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$ dut-control spi2_vref:off spi2_buf_en:off spi2_buf_on_flex_en:off warm_reset:off
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```
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### References
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* [flashrom](https://flashrom.org/Flashrom)
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* [Servo](https://www.chromium.org/chromium-os/servo)
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@ -2,6 +2,10 @@
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This section contains documentation about coreboot on specific Intel "Ice Lake" SOCs.
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## Ice Lake coreboot development
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- [Ice Lake coreboot development](iceLake_coreboot_development.md)
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## Multiprocessor Init
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- [Multiprocessor Init](MultiProcessorInit.md)
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