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soc/intel/alderlake: Add tpch device information under dptf 

Add tpch device information for thermal functionality under dptf
for alderlake soc based platform.

BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board

Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sumeet Pawnikar 2021-08-31 21:19:56 +05:30 committed by Felix Held
parent a91d931114
commit 92db5d734c
1 changed files with 6 additions and 0 deletions
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6
src/soc/intel/alderlake/dptf.c
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@ -10,6 +10,12 @@ static const struct dptf_platform_info adl_dptf_platform_info = {
.generic_hid = "INTC1046",
/* _HID for Intel DPTF Fan Device */
.fan_hid = "INTC1048",
/* _HID for the toplevel TPCH device, typically \_SB.TPCH */
.tpch_device_hid = "INTC1049",
/* RFC0 method name */
.tpch_rfc0_method = "RFC0",
/* RFC1 method name */
.tpch_rfc1_method = "RFC1",
};
const struct dptf_platform_info *get_dptf_platform_info(void)