GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/cezanne: Add soc/msr.h 

This is a copy of picasso.

BUG=b:184151560
TEST=Compared with the cezanne PPR.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia4bc40daa971c126c2596837155312d411b91a06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Raul E Rangel 2021-03-31 13:15:07 -06:00 committed by Martin Roth
parent 7a347afa95
commit 92e66cc4e3
1 changed files with 24 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/soc/amd/cezanne/include/soc/msr.h Normal file
View File

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef AMD_CEZANNE_MSR_H
#define AMD_CEZANNE_MSR_H
/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
#define PSTATE_DEF_HI_ENABLE_SHIFT 31
#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT)
#define PSTATE_DEF_LO_CUR_DIV_SHIFT 30
#define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT)
#define PSTATE_DEF_LO_CUR_VAL_SHIFT 22
#define PSTATE_DEF_LO_CUR_VAL_MASK (0xFF << PSTATE_DEF_LO_CUR_VAL_SHIFT)
#define PSTATE_DEF_LO_CORE_VID_SHIFT 14
#define PSTATE_DEF_LO_CORE_VID_MASK (0xFF << PSTATE_DEF_LO_CORE_VID_SHIFT)
#define PSTATE_DEF_LO_FREQ_DIV_SHIFT 8
#define PSTATE_DEF_LO_FREQ_DIV_MASK (0x3F << PSTATE_DEF_LO_FREQ_DIV_SHIFT)
#define PSTATE_DEF_LO_FREQ_DIV_MIN 0x8
#define PSTATE_DEF_LO_EIGHTH_STEP_MAX 0x1A
#define PSTATE_DEF_LO_FREQ_DIV_MAX 0x3E
#define PSTATE_DEF_LO_FREQ_MUL_SHIFT 0
#define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT)
#define PSTATE_DEF_LO_CORE_FREQ_BASE 25
#endif /* AMD_CEZANNE_MSR_H */