soc/baytrail: assign unique DMA request lines to I2C controllers
Each I2C controller should have a unique pair of DMA request lines, and DMA channels should be assigned incrementally, rolling over as necessary. Source: Intel Baytrail/ValleyView UEFI reference code Change-Id: Icc9b27aaa14583d11d325e43d9165ddda72ca865 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -156,8 +156,8 @@ Device (I2C2)
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{
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{
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LPSS_I2C2_IRQ
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LPSS_I2C2_IRQ
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}
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}
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FixedDMA (0x10, 0x0, Width32Bit, )
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FixedDMA (0x12, 0x2, Width32Bit, )
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FixedDMA (0x11, 0x1, Width32Bit, )
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FixedDMA (0x13, 0x3, Width32Bit, )
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})
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})
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Method (_CRS)
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Method (_CRS)
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@ -215,8 +215,8 @@ Device (I2C3)
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{
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{
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LPSS_I2C3_IRQ
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LPSS_I2C3_IRQ
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}
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}
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FixedDMA (0x10, 0x0, Width32Bit, )
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FixedDMA (0x14, 0x4, Width32Bit, )
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FixedDMA (0x11, 0x1, Width32Bit, )
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FixedDMA (0x15, 0x5, Width32Bit, )
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})
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})
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Method (_CRS)
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Method (_CRS)
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@ -274,8 +274,8 @@ Device (I2C4)
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{
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{
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LPSS_I2C4_IRQ
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LPSS_I2C4_IRQ
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}
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}
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FixedDMA (0x10, 0x0, Width32Bit, )
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FixedDMA (0x16, 0x6, Width32Bit, )
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FixedDMA (0x11, 0x1, Width32Bit, )
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FixedDMA (0x17, 0x7, Width32Bit, )
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})
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})
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Method (_CRS)
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Method (_CRS)
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@ -333,8 +333,8 @@ Device (I2C5)
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{
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{
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LPSS_I2C5_IRQ
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LPSS_I2C5_IRQ
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}
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}
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FixedDMA (0x10, 0x0, Width32Bit, )
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FixedDMA (0x18, 0x0, Width32Bit, )
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FixedDMA (0x11, 0x1, Width32Bit, )
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FixedDMA (0x19, 0x1, Width32Bit, )
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})
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})
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Method (_CRS)
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Method (_CRS)
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@ -392,8 +392,8 @@ Device (I2C6)
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{
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{
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LPSS_I2C6_IRQ
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LPSS_I2C6_IRQ
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}
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}
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FixedDMA (0x10, 0x0, Width32Bit, )
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FixedDMA (0x1A, 0x2, Width32Bit, )
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FixedDMA (0x11, 0x1, Width32Bit, )
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FixedDMA (0x1B, 0x3, Width32Bit, )
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})
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})
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Method (_CRS)
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Method (_CRS)
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@ -451,8 +451,8 @@ Device (I2C7)
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{
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{
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LPSS_I2C7_IRQ
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LPSS_I2C7_IRQ
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}
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}
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FixedDMA (0x10, 0x0, Width32Bit, )
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FixedDMA (0x1C, 0x4, Width32Bit, )
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FixedDMA (0x11, 0x1, Width32Bit, )
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FixedDMA (0x1D, 0x5, Width32Bit, )
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})
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})
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Method (_CRS)
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Method (_CRS)
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