From 93078ba1ae144304a19c83ae7d565cb2c39c1d15 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 18 Jun 2021 12:56:21 +0000 Subject: [PATCH] Revert "soc/intel/broadwell/pch: Drop device NVS remainders" This reverts commit 34bd6ba97917b0bc54bb1f1e106a56b5c03e19ac. Reason for revert: Device NVS is expected by mainboard samus in payload depthcharge: https://chromium.googlesource.com/chromiumos/platform/depthcharge/+/932c6ba2704987c0db64dbdfe03c158482c7ab11/src/board/samus/board.c#60 Not reverted: * ACPI_HAS_DEVICE_NVS does not exist anymore in ToT and hence it's selection in broadwell is not required. Signed-off-by: Furquan Shaikh Change-Id: Ic31d7ae62c5df72708b724160e96e10b46002eb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54976 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../intel/broadwell/include/soc/device_nvs.h | 24 +++++++ src/soc/intel/broadwell/include/soc/pch.h | 21 ------ src/soc/intel/broadwell/pch/acpi.c | 42 +++++------- src/soc/intel/broadwell/pch/adsp.c | 14 ++-- src/soc/intel/broadwell/pch/serialio.c | 67 +++++++++++-------- 5 files changed, 89 insertions(+), 79 deletions(-) create mode 100644 src/soc/intel/broadwell/include/soc/device_nvs.h diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h new file mode 100644 index 0000000000..27304b573d --- /dev/null +++ b/src/soc/intel/broadwell/include/soc/device_nvs.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _BROADWELL_DEVICE_NVS_H_ +#define _BROADWELL_DEVICE_NVS_H_ + +#include + +#define SIO_NVS_DMA 0 +#define SIO_NVS_I2C0 1 +#define SIO_NVS_I2C1 2 +#define SIO_NVS_SPI0 3 +#define SIO_NVS_SPI1 4 +#define SIO_NVS_UART0 5 +#define SIO_NVS_UART1 6 +#define SIO_NVS_SDIO 7 +#define SIO_NVS_ADSP 8 + +struct __packed device_nvs { + u8 enable[9]; + u32 bar0[9]; + u32 bar1[9]; +}; + +#endif diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/soc/intel/broadwell/include/soc/pch.h index 8367a39b7f..8089f5bdb0 100644 --- a/src/soc/intel/broadwell/include/soc/pch.h +++ b/src/soc/intel/broadwell/include/soc/pch.h @@ -4,7 +4,6 @@ #define _BROADWELL_PCH_H_ #include -#include /* Haswell ULT Pch (LynxPoint-LP) */ #define PCH_LPT_LP_SAMPLE 0x9c41 @@ -26,25 +25,6 @@ #define PCH_PCS 0x84 #define PCH_PCS_PS_D3HOT 3 -enum pch_acpi_device { - PCH_ACPI_SDMA = 0, - PCH_ACPI_I2C0, - PCH_ACPI_I2C1, - PCH_ACPI_GSPI0, - PCH_ACPI_GSPI1, - PCH_ACPI_UART0, - PCH_ACPI_UART1, - PCH_ACPI_SDIO, - PCH_ACPI_ADSP, - NUM_PCH_ACPI_DEVICES, -}; - -struct pch_acpi_device_state { - bool enable; - uint32_t bar0; - uint32_t bar1; -}; - u8 pch_revision(void); u16 pch_type(void); int pch_is_wpt(void); @@ -52,7 +32,6 @@ int pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); void pch_disable_devfn(struct device *dev); -struct pch_acpi_device_state *get_acpi_device_state(enum pch_acpi_device dev_index); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void broadwell_pch_finalize(void); diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c index 8c435d6f47..85726b06e4 100644 --- a/src/soc/intel/broadwell/pch/acpi.c +++ b/src/soc/intel/broadwell/pch/acpi.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include -#include +#include #include #include #include @@ -54,32 +55,25 @@ static void acpi_write_serialio_psx_methods(const char *const name, const uint32 acpigen_pop_len(); } -static struct pch_acpi_device_state device_state[NUM_PCH_ACPI_DEVICES] = { 0 }; - -struct pch_acpi_device_state *get_acpi_device_state(enum pch_acpi_device dev_index) +static void acpi_create_serialio_ssdt_entry(int sio_index, struct device_nvs *dev_nvs) { - assert(dev_index < ARRAY_SIZE(device_state)); - return &device_state[dev_index]; -} - -static void acpi_create_serialio_ssdt_entry(enum pch_acpi_device dev_index) -{ - const struct pch_acpi_device_state *state = get_acpi_device_state(dev_index); - - const char idx = '0' + dev_index; + const char idx = '0' + sio_index; const char sxen[5] = { 'S', idx, 'E', 'N', '\0' }; - acpigen_write_name_byte(sxen, state->enable); + acpigen_write_name_byte(sxen, dev_nvs->enable[sio_index]); const char sxb0[5] = { 'S', idx, 'B', '0', '\0' }; - acpigen_write_name_dword(sxb0, state->bar0); + acpigen_write_name_dword(sxb0, dev_nvs->bar0[sio_index]); const char sxb1[5] = { 'S', idx, 'B', '1', '\0' }; - acpigen_write_name_dword(sxb1, state->bar1); + acpigen_write_name_dword(sxb1, dev_nvs->bar1[sio_index]); } void acpi_create_serialio_ssdt(acpi_header_t *ssdt) { unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); + struct device_nvs *dev_nvs = acpi_get_device_nvs(); + if (!dev_nvs) + return; /* Fill the SSDT header */ memset((void *)ssdt, 0, sizeof(acpi_header_t)); @@ -94,17 +88,17 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt) acpigen_set_current((char *)current); /* Fill the SSDT with an entry for each SerialIO device */ - for (enum pch_acpi_device dev_index = 0; dev_index < NUM_PCH_ACPI_DEVICES; dev_index++) - acpi_create_serialio_ssdt_entry(dev_index); + for (int id = 0; id < 9; id++) + acpi_create_serialio_ssdt_entry(id, dev_nvs); acpigen_write_scope("\\_SB.PCI0"); { - acpi_write_serialio_psx_methods("I2C0", device_state[PCH_ACPI_I2C0].bar1); - acpi_write_serialio_psx_methods("I2C1", device_state[PCH_ACPI_I2C1].bar1); - acpi_write_serialio_psx_methods("SPI0", device_state[PCH_ACPI_GSPI0].bar1); - acpi_write_serialio_psx_methods("SPI1", device_state[PCH_ACPI_GSPI1].bar1); - acpi_write_serialio_psx_methods("UAR0", device_state[PCH_ACPI_UART0].bar1); - acpi_write_serialio_psx_methods("UAR1", device_state[PCH_ACPI_UART1].bar1); + acpi_write_serialio_psx_methods("I2C0", dev_nvs->bar1[SIO_NVS_I2C0]); + acpi_write_serialio_psx_methods("I2C1", dev_nvs->bar1[SIO_NVS_I2C1]); + acpi_write_serialio_psx_methods("SPI0", dev_nvs->bar1[SIO_NVS_SPI0]); + acpi_write_serialio_psx_methods("SPI1", dev_nvs->bar1[SIO_NVS_SPI1]); + acpi_write_serialio_psx_methods("UAR0", dev_nvs->bar1[SIO_NVS_UART0]); + acpi_write_serialio_psx_methods("UAR1", dev_nvs->bar1[SIO_NVS_UART1]); } acpigen_pop_len(); diff --git a/src/soc/intel/broadwell/pch/adsp.c b/src/soc/intel/broadwell/pch/adsp.c index 3cc7e12f2a..1ebf922aec 100644 --- a/src/soc/intel/broadwell/pch/adsp.c +++ b/src/soc/intel/broadwell/pch/adsp.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -7,6 +8,8 @@ #include #include #include +#include +#include #include #include #include @@ -75,14 +78,15 @@ static void adsp_init(struct device *dev) pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE); if (config->sio_acpi_mode) { + struct device_nvs *dev_nvs = acpi_get_device_nvs(); + /* Configure for ACPI mode */ printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n"); - /* Save BAR0 and BAR1 */ - struct pch_acpi_device_state *state = get_acpi_device_state(PCH_ACPI_ADSP); - state->enable = 1; - state->bar0 = (u32)bar0->base; - state->bar1 = (u32)bar1->base; + /* Save BAR0 and BAR1 to ACPI NVS */ + dev_nvs->bar0[SIO_NVS_ADSP] = (u32)bar0->base; + dev_nvs->bar1[SIO_NVS_ADSP] = (u32)bar1->base; + dev_nvs->enable[SIO_NVS_ADSP] = 1; /* Set PCI Config Disable Bit */ pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~0, ADSP_PCICFGCTL_PCICD); diff --git a/src/soc/intel/broadwell/pch/serialio.c b/src/soc/intel/broadwell/pch/serialio.c index 601bf97629..e38de5eda1 100644 --- a/src/soc/intel/broadwell/pch/serialio.c +++ b/src/soc/intel/broadwell/pch/serialio.c @@ -2,10 +2,12 @@ #include #include +#include #include #include #include #include +#include #include #include #include @@ -156,7 +158,7 @@ static void serialio_init(struct device *dev) { const struct soc_intel_broadwell_pch_config *config = config_of(dev); struct resource *bar0, *bar1; - enum pch_acpi_device dev_index = NUM_PCH_ACPI_DEVICES; + int sio_index = -1; printk(BIOS_DEBUG, "Initializing Serial IO device\n"); @@ -175,48 +177,54 @@ static void serialio_init(struct device *dev) serialio_enable_clock(bar0); switch (dev->path.pci.devfn) { - case PCH_DEVFN_SDMA: - dev_index = PCH_ACPI_SDMA; + case PCH_DEVFN_SDMA: /* SDMA */ + sio_index = SIO_ID_SDMA; serialio_init_once(config->sio_acpi_mode); - serialio_d21_mode(SIO_ID_SDMA, SIO_PIN_INTB, + serialio_d21_mode(sio_index, SIO_PIN_INTB, config->sio_acpi_mode); break; - case PCH_DEVFN_I2C0: - dev_index = PCH_ACPI_I2C0; + case PCH_DEVFN_I2C0: /* I2C0 */ + sio_index = SIO_ID_I2C0; serialio_d21_ltr(bar0); serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage); - serialio_d21_mode(SIO_ID_I2C0, SIO_PIN_INTC, config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTC, + config->sio_acpi_mode); break; - case PCH_DEVFN_I2C1: - dev_index = PCH_ACPI_I2C1; + case PCH_DEVFN_I2C1: /* I2C1 */ + sio_index = SIO_ID_I2C1; serialio_d21_ltr(bar0); serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage); - serialio_d21_mode(SIO_ID_I2C1, SIO_PIN_INTC, config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTC, + config->sio_acpi_mode); break; - case PCH_DEVFN_SPI0: - dev_index = PCH_ACPI_GSPI0; + case PCH_DEVFN_SPI0: /* SPI0 */ + sio_index = SIO_ID_SPI0; serialio_d21_ltr(bar0); - serialio_d21_mode(SIO_ID_SPI0, SIO_PIN_INTC, config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTC, + config->sio_acpi_mode); break; - case PCH_DEVFN_SPI1: - dev_index = PCH_ACPI_GSPI1; + case PCH_DEVFN_SPI1: /* SPI1 */ + sio_index = SIO_ID_SPI1; serialio_d21_ltr(bar0); - serialio_d21_mode(SIO_ID_SPI1, SIO_PIN_INTC, config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTC, + config->sio_acpi_mode); break; - case PCH_DEVFN_UART0: - dev_index = PCH_ACPI_UART0; + case PCH_DEVFN_UART0: /* UART0 */ + sio_index = SIO_ID_UART0; if (!serialio_uart_is_debug(dev)) serialio_d21_ltr(bar0); - serialio_d21_mode(SIO_ID_UART0, SIO_PIN_INTD, config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTD, + config->sio_acpi_mode); break; - case PCH_DEVFN_UART1: - dev_index = PCH_ACPI_UART1; + case PCH_DEVFN_UART1: /* UART1 */ + sio_index = SIO_ID_UART1; if (!serialio_uart_is_debug(dev)) serialio_d21_ltr(bar0); - serialio_d21_mode(SIO_ID_UART1, SIO_PIN_INTD, config->sio_acpi_mode); + serialio_d21_mode(sio_index, SIO_PIN_INTD, + config->sio_acpi_mode); break; - case PCH_DEVFN_SDIO: - dev_index = PCH_ACPI_SDIO; + case PCH_DEVFN_SDIO: /* SDIO */ + sio_index = SIO_ID_SDIO; serialio_d23_ltr(bar0); serialio_d23_mode(config->sio_acpi_mode); break; @@ -225,14 +233,15 @@ static void serialio_init(struct device *dev) } if (config->sio_acpi_mode) { - /* Save BAR0 and BAR1 */ - struct pch_acpi_device_state *state = get_acpi_device_state(dev_index); - state->bar0 = (u32)bar0->base; - state->bar1 = (u32)bar1->base; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); + + /* Save BAR0 and BAR1 to ACPI NVS */ + dev_nvs->bar0[sio_index] = (u32)bar0->base; + dev_nvs->bar1[sio_index] = (u32)bar1->base; if (!serialio_uart_is_debug(dev)) { /* Do not enable UART if it is used as debug port */ - state->enable = 1; + dev_nvs->enable[sio_index] = 1; /* Put device in D3hot state via BAR1 */ if (dev->path.pci.devfn != PCH_DEVFN_SDMA)