From 930b643f8f76a63ab60bf0239a7da8713f3ff619 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 7 Jun 2021 20:04:55 +0530 Subject: [PATCH] soc/intel/alderlake/romstage: Drop ineffective FSP-M UPD `ChHashMask` FSP-M UPD ChHashOverride is default disable hence ChHashMask doesn't take any effect. Dropping ChHashMask assignment in coreboot. TEST=Able to build and boot ADL-P LP4 RVP. FSP-M UPD dump showed both UPDs are set to default value 0. ChHashOverride: 0 ChHashMask: 0h Change-Id: Ide1c9da27ca68fd36ff5b44910cfcedfcb12f232 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/55272 Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/romstage/fsp_params.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index abfc1d91ee..3892f25477 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -128,8 +128,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->HyperThreading = 1; /* Disable Lock PCU Thermal Management registers */ m_cfg->LockPTMregs = 0; - /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ - m_cfg->ChHashMask = 0x30CC; /* Enable SMBus controller */ dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); m_cfg->SmbusEnable = is_dev_enabled(dev);