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mb/system76/rpl: Add Gazelle 18 

The Gazelle 18 (gaze18) is a Raptor Lake-H board.

Tested with a custom TianoCore UefiPayloadPkg.

Working:

- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots
- M.2 NVMe SSD slot
- M.2 SATA SSD slot
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.6

Not working:

- Discrete/Hybrid graphics

Change-Id: I4599bf12c0f3048f9328f336cc8971400f5fd1a0
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
This commit is contained in:
Tim Crawford 2023-05-16 12:41:31 -06:00 committed by Felix Held
parent 2049bb9b2c
commit 930dbc0d04
24 changed files with 812 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/mainboard/index.md
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@ -214,6 +214,7 @@ The boards in this section are not real mainboards, but emulators.
- [Galago Pro 6](system76/galp6.md)
- [Gazelle 15](system76/gaze15.md)
- [Gazelle 16](system76/gaze16.md)
- [Gazelle 18](system76/gaze18.md)
- [Lemur Pro 9](system76/lemp9.md)
- [Lemur Pro 10](system76/lemp10.md)
- [Lemur Pro 11](system76/lemp11.md)

72
Documentation/mainboard/system76/gaze18.md Normal file
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# System76 Gazelle 18 (gaze18)
## Specs
- CPU
- Intel i9-13900H
- Chipset
- Intel HM770
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- NVIDIA GeForce RTX 3050 (70W TDP)
- Intel Irix Xe Graphics
- eDP displays
- 17.3" 1920x1080@144Hz LCD
- 15.6" 1920x1080@144Hz LCD
- External outputs
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
- Networking
- Realtek RTL8111H gigabit Ethernet
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6E AX210/AX211
- Power
- 150W AC barrel adapter
- Included: LiteOn PA-1151-76, using a C5 power cord
- 54Wh 4-cell battery (NP50BAT-4-54)
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- Dedicated 3.5mm microphone jack
- HDMI, mDP audio
- Storage
- 1x M.2 (PCIe NVMe Gen 4)
- 1x M.2 (PCIe NVMe Gen 3)
- MicroSD card reader
- Realtek RTS5227S
- USB
- 2x USB 3.2 Gen 2 Type-C
- Does not support USB-C charging (USB-PD) or Thunderbolt
- 1x USB 3.2 Gen 2 Type-A
- 1x USB 2.0 Type-A
- Dimensions
- 15": 35.95cm x 23.8cm x 2.27cm, 1.99kg
- 17": 39.69cm x 26.2cm x 2.5cm, 2.41kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U24) is right of the M.2 SSD connectors.

80
src/mainboard/system76/rpl/Kconfig Normal file
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@ -0,0 +1,80 @@
config BOARD_SYSTEM76_RPL_COMMON
def_bool n
select BOARD_ROMSIZE_KB_32768
select DRIVERS_I2C_HID
select EC_SYSTEM76_EC
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_TPM2
select MEMORY_MAPPED_TPM
select NO_UART_ON_SUPERIO
select PCIEXP_SUPPORT_RESIZABLE_BARS
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_CRASHLOG
select SOC_INTEL_RAPTORLAKE
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
select TPM_RDRESP_NEED_DELAY
config BOARD_SYSTEM76_GAZE18
select BOARD_SYSTEM76_RPL_COMMON
select EC_SYSTEM76_EC_COLOR_KEYBOARD
select EC_SYSTEM76_EC_DGPU
select SOC_INTEL_ALDERLAKE_PCH_P
if BOARD_SYSTEM76_RPL_COMMON
config MAINBOARD_DIR
default "system76/rpl"
config VARIANT_DIR
default "gaze18" if BOARD_SYSTEM76_GAZE18
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAINBOARD_PART_NUMBER
default "gaze18" if BOARD_SYSTEM76_GAZE18
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Gazelle" if BOARD_SYSTEM76_GAZE18
config MAINBOARD_VERSION
default "gaze18" if BOARD_SYSTEM76_GAZE18
config CONSOLE_POST
default y
config D3COLD_SUPPORT
default n
config DIMM_SPD_SIZE
default 512
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
config ONBOARD_VGA_IS_PRIMARY
default y
config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
default 36
config POST_DEVICE
default n
config TPM_MEASURED_BOOT
default y
config UART_FOR_CONSOLE
default 0
# PM Timer Disabled, saves power
config USE_PM_ACPI_TIMER
default n
endif

2
src/mainboard/system76/rpl/Kconfig.name Normal file
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config BOARD_SYSTEM76_GAZE18
bool "gaze18"

10
src/mainboard/system76/rpl/Makefile.inc Normal file
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@ -0,0 +1,10 @@
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
romstage-y += variants/$(VARIANT_DIR)/romstage.c
ramstage-y += ramstage.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ramstage-y += variants/$(VARIANT_DIR)/gpio.c

31
src/mainboard/system76/rpl/acpi/backlight.asl Normal file
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@ -0,0 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/intel/gma/acpi/gma.asl>
Scope (GFX0)
{
Name (BRIG, Package (22) {
40, /* default AC */
40, /* default Battery */
5,
10,
15,
20,
25,
30,
35,
40,
45,
50,
55,
60,
65,
70,
75,
80,
85,
90,
95,
100
})
}

12
src/mainboard/system76/rpl/acpi/mainboard.asl Normal file
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@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#define EC_GPE_SCI 0x6E
#define EC_GPE_SWI 0x6B
#include <ec/system76/ec/acpi/ec.asl>
Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
#include "backlight.asl"
}
}

9
src/mainboard/system76/rpl/acpi/sleep.asl Normal file
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@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
External(\TBTS, MethodObj)
Method(MPTS, 1, Serialized) {
If (CondRefOf(\TBTS)) {
\TBTS()
}
}

6
src/mainboard/system76/rpl/board_info.txt Normal file
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@ -0,0 +1,6 @@
Vendor name: System76
Category: laptop
ROM package: WSON-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y

9
src/mainboard/system76/rpl/bootblock.c Normal file
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@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <mainboard/gpio.h>
void bootblock_mainboard_early_init(void)
{
mainboard_configure_early_gpios();
}

3
src/mainboard/system76/rpl/cmos.default Normal file
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@ -0,0 +1,3 @@
boot_option=Fallback
debug_level=Debug
me_state=Disable

39
src/mainboard/system76/rpl/cmos.layout Normal file
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@ -0,0 +1,39 @@
# SPDX-License-Identifier: GPL-2.0-only
entries
0 384 r 0 reserved_memory
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# RTC_CLK_ALTCENTURY
400 8 r 0 century
412 4 e 6 debug_level
416 1 e 2 me_state
417 3 h 0 me_state_counter
984 16 h 0 check_sum
enumerations
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 408 983 984

72
src/mainboard/system76/rpl/devicetree.cb Normal file
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@ -0,0 +1,72 @@
chip soc/intel/alderlake
register "common_soc_config" = "{
// Touchpad I2C bus
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
.fall_time_ns = 110,
},
}"
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "1"
# Enable C6 DRAM
register "enable_c6dram" = "1"
# Thermal
register "tcc_offset" = "8"
device cpu_cluster 0 on end
device domain 0 on
device ref system_agent on end
device ref igpu on
# DDIA is eDP, DDIB is HDMI
register "ddi_portA_config" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD,
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device ref shared_sram on end
device ref cnvi_wifi on
register "cnvi_bt_core" = "true"
register "cnvi_bt_audio_offload" = "true"
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref i2c1 on
register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
end
device ref heci1 on end
device ref sata on
register "sata_salp_support" = "1"
register "sata_ports_enable[1]" = "1" # SSD1
# FIXME: DevSlp breaks S0ix
#register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1)
end
device ref pch_espi on
register "gen1_dec" = "0x00040069" # EC PM channel
register "gen2_dec" = "0x00fc0e01" # AP/EC command
register "gen3_dec" = "0x00fc0f01" # AP/EC debug
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device ref p2sb on end
device ref hda on
register "pch_hda_audio_link_hda_enable" = "1"
register "pch_hda_idisp_codec_enable" = "1"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
end
device ref smbus on end
device ref fast_spi on end
end
end

32
src/mainboard/system76/rpl/dsdt.asl Normal file
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@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725
)
{
#include <acpi/dsdt_top.asl>
#include <soc/intel/common/block/acpi/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Device (\_SB.PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/alderlake/acpi/southbridge.asl>
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/pc/ps2_controller.asl>
}
#include "acpi/mainboard.asl"
}

9
src/mainboard/system76/rpl/include/mainboard/gpio.h Normal file
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@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
void mainboard_configure_early_gpios(void);
void mainboard_configure_gpios(void);
#endif

21
src/mainboard/system76/rpl/ramstage.c Normal file
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@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/ramstage.h>
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
// TODO: Pin Mux settings
// Enable reporting CPU C10 state over eSPI.
params->PchEspiHostC10ReportEnable = 1;
}
static void mainboard_init(void *chip_info)
{
mainboard_configure_gpios();
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
};

12
src/mainboard/system76/rpl/variants/gaze18/board.fmd Normal file
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@ -0,0 +1,12 @@
FLASH 32M {
SI_DESC 4K
SI_ME 4824K
SI_BIOS@16M 16M {
RW_MRC_CACHE 64K
SMMSTORE(PRESERVE) 256K
WP_RO {
FMAP 4K
COREBOOT(CBFS)
}
}
}

2
src/mainboard/system76/rpl/variants/gaze18/board_info.txt Normal file
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@ -0,0 +1,2 @@
Board name: gaze18
Release year: 2023

BIN
src/mainboard/system76/rpl/variants/gaze18/data.vbt Normal file
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Binary file not shown.

227
src/mainboard/system76/rpl/variants/gaze18/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
PAD_NC(GPD7, NONE),
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // Not documented
PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
PAD_NC(GPD11, NONE),
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
PAD_NC(GPP_A6, NONE),
PAD_NC(GPP_A7, NONE),
PAD_CFG_GPO(GPP_A8, 1, PLTRST), // SATA_PWR_EN
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N
PAD_NC(GPP_A11, NONE),
PAD_NC(GPP_A12, NONE),
PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
// GPP_A14 (DGPU_PWR_EN) configured in bootblock
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // MDP_B_HPD
PAD_NC(GPP_A16, NONE), // USB_OC3#
PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
PAD_CFG_GPO(GPP_A20, 0, DEEP), // PEX_WAKE#
PAD_NC(GPP_A21, NONE),
PAD_NC(GPP_A22, NONE),
PAD_NC(GPP_A23, NONE),
/* ------- GPIO Group GPP_B ------- */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
// GPP_B2 (DGPU_RST#_PCH) configured in bootblock
PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
PAD_NC(GPP_B5, NONE),
PAD_NC(GPP_B6, NONE),
PAD_NC(GPP_B7, NONE),
PAD_NC(GPP_B8, NONE),
// GPP_B9 missing
// GPP_B10 missing
PAD_NC(GPP_B11, NONE),
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // BUF_PLT_RST#
PAD_NC(GPP_B14, NONE), // TOP SWAP OVERRIDE strap
PAD_NC(GPP_B15, NONE),
PAD_NC(GPP_B16, NONE),
PAD_NC(GPP_B17, NONE),
PAD_NC(GPP_B18, NONE), // NO REBOOT strap
// GPP_B19 missing
// GPP_B20 missing
// GPP_B21 missing
// GPP_B22 missing
PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2
PAD_NC(GPP_C3, NONE),
PAD_NC(GPP_C4, NONE),
PAD_NC(GPP_C5, NONE), // TLS CONFIDENTIALITY strap
PAD_NC(GPP_C6, NONE),
PAD_NC(GPP_C7, NONE),
// GPP_C8 missing
// GPP_C9 missing
// GPP_C10 missing
// GPP_C11 missing
// GPP_C12 missing
// GPP_C13 missing
// GPP_C14 missing
// GPP_C15 missing
// GPP_C16 missing
// GPP_C17 missing
// GPP_C18 missing
// GPP_C19 missing
// GPP_C20 missing
// GPP_C21 missing
// GPP_C22 missing
// GPP_C23 missing
/* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
PAD_NC(GPP_D2, NONE),
PAD_NC(GPP_D3, NONE),
PAD_CFG_GPI(GPP_D4, NONE, DEEP), // GPIO_LAN_EN
// GPP_D5 (SSD0_CLKREQ#) configured by FSP
// GPP_D6 (SSD1_CLKREQ#) configured by FSP
// GPP_D7 (WLAN_CLKREQ#) configured by FSP
// GPP_D8 (GPU_PCIE_CLKREQ#) configured by FSP
PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE),
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2), // I_MDP_CLK
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF2), // I_MDP_DATA
PAD_NC(GPP_D13, NONE),
PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1
PAD_CFG_GPO(GPP_D15, 0, DEEP), // LANRTD3_WAKE#
PAD_CFG_GPO(GPP_D16, 1, PLTRST), // LAN_RTD3_EN#
PAD_NC(GPP_D17, NONE),
PAD_NC(GPP_D18, NONE),
PAD_NC(GPP_D19, NONE),
/* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
PAD_NC(GPP_E2, NONE), // BOARD_ID2
PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
PAD_NC(GPP_E4, NONE),
PAD_NC(GPP_E5, NONE),
PAD_NC(GPP_E6, NONE), // JTAG ODT DISABLE strap
PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
PAD_NC(GPP_E9, NONE), // USB_OC0#
PAD_CFG_GPO(GPP_E10, 0, DEEP), // KBLED_DET
PAD_NC(GPP_E11, NONE), // BOARD_ID1
PAD_NC(GPP_E12, NONE),
PAD_NC(GPP_E13, NONE), // BOARD_ID4
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_E15, 0, DEEP),
PAD_CFG_GPO(GPP_E16, 0, DEEP),
PAD_NC(GPP_E17, NONE), // BOARD_ID3
PAD_NC(GPP_E18, NONE),
PAD_NC(GPP_E19, NONE), // strap
PAD_NC(GPP_E20, NONE),
PAD_NC(GPP_E21, NONE), // strap
PAD_NC(GPP_E22, NONE),
PAD_NC(GPP_E23, NONE),
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
// GPP_F5 (CNVI_CLKREQ) configured by FSP
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
// GPP_F8 missing
PAD_NC(GPP_F9, NONE),
PAD_CFG_GPO(GPP_F10, 0, DEEP), // PCIE_GLAN_RST#
PAD_NC(GPP_F11, NONE),
PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R
PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
PAD_NC(GPP_F14, NONE), // LIGHT_KB_DET#
PAD_NC(GPP_F15, NONE),
PAD_CFG_GPO(GPP_F16, 0, DEEP), // GPU_EVENT#
PAD_NC(GPP_F17, NONE),
PAD_CFG_GPO(GPP_F18, 0, DEEP), // DGPU_OVRM
// GPP_F19 (GLAN_CLKREQ#) configured by FSP
PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
PAD_NC(GPP_F21, NONE),
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), // VNN_CTRL
PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), // V1P05_CTRL
/* ------- GPIO Group GPP_H ------- */
PAD_NC(GPP_H0, NONE),
PAD_CFG_GPO(GPP_H1, 0, DEEP), // M.2_PLT_RST_CNTRL2#
PAD_CFG_GPO(GPP_H2, 0, DEEP), // M.2_PLT_RST_CNTRL3#
PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
PAD_NC(GPP_H6, NONE),
PAD_NC(GPP_H7, NONE),
PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
// GPP_H10 (UART0_RX) configured in bootblock
// GPP_H11 (UART0_TX) configured in bootblock
PAD_NC(GPP_H12, NONE),
_PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000), // DEVSLP1
// GPP_H14 missing
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
// GPP_H16 missing
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
PAD_NC(GPP_H19, NONE),
PAD_NC(GPP_H20, NONE),
PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE),
// GPP_H23 (CARD_CLKREQ#) configured by FSP
/* ------- GPIO Group GPP_R ------- */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R
PAD_NC(GPP_R5, NONE),
PAD_NC(GPP_R6, NONE),
PAD_NC(GPP_R7, NONE),
/* ------- GPIO Group GPP_S ------- */
PAD_NC(GPP_S0, NONE),
PAD_NC(GPP_S1, NONE),
PAD_NC(GPP_S2, NONE),
PAD_NC(GPP_S3, NONE),
PAD_NC(GPP_S4, NONE),
PAD_NC(GPP_S5, NONE),
PAD_NC(GPP_S6, NONE),
PAD_NC(GPP_S7, NONE),
/* ------- GPIO Group GPP_T ------- */
PAD_NC(GPP_T2, NONE),
PAD_NC(GPP_T3, NONE),
};
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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src/mainboard/system76/rpl/variants/gaze18/gpio_early.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
};
void mainboard_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

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src/mainboard/system76/rpl/variants/gaze18/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC256 */
0x10ec0256, /* Vendor ID */
0x15585630, /* Subsystem ID */
12, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x15585630),
AZALIA_RESET(1),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

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src/mainboard/system76/rpl/variants/gaze18/overridetree.cb Normal file
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chip soc/intel/alderlake
device domain 0 on
subsystemid 0x1558 0x5630 inherit
device ref xhci on
# USB2
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_TYPEC1 (USB 3.1 Gen2)
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A (USB 3.1 Gen2)
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # J_TYPEC2 (USB 3.1 Gen2)
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Finger
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A (USB 3.1 Gen2)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
end
device ref i2c0 on
# Touchpad I2C bus
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid
register "generic.hid" = ""ELAN0412""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""FTCS1000""
register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 38 on end
end
end
device ref pcie5_0 on
# CPU PCIe RP#2 x8, Clock 3 (GPU)
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie4_0 on
# CPU RP#1 x4, Clock 0 (SSD0)
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp5 on
# PCH RP#5 x4, Clock 1 (SSD1)
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp9 on
# PCH RP#9 x1, Clock 6 (GLAN)
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
device pci 00.0 on end
end
device ref pcie_rp10 on
# PCH RP#10 x1, Clock 2 (WLAN)
register "pch_pcie_rp[PCH_RP(10)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp11 on
# PCH RP#11 x1, Clock 5 (CARD)
register "pch_pcie_rp[PCH_RP(11)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
end
end

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src/mainboard/system76/rpl/variants/gaze18/romstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/meminit.h>
#include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR5,
.ect = true,
.LpDdrDqDqsReTraining = 1,
};
const struct mem_spd spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = { .addr_dimm[0] = 0x50, },
[1] = { .addr_dimm[0] = 0x52, },
},
};
const bool half_populated = false;
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
}