From 93197d20b65002fcd09fd9ed82f5c644aab0c352 Mon Sep 17 00:00:00 2001
From: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Date: Mon, 12 Dec 2022 15:23:19 +0800
Subject: [PATCH] mb/google/brya/var/marasov: Disable unused PCIE8 for s0ix

Disable unused PCIE8 for fix system can not enter S0ix completely.

BUG=b:261915226
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I06f8bd06e1fe92c03bd5625a41469830ce37a11c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70660
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/brya/variants/marasov/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb
index 63899cef23..832554e65c 100644
--- a/src/mainboard/google/brya/variants/marasov/overridetree.cb
+++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb
@@ -182,6 +182,7 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end
+		device ref pcie_rp8 off end
 		device ref pcie_rp11 on
 			# Enable NVMe SSD PCIe 11-12 using clk 1
 			register "pch_pcie_rp[PCH_RP(11)]" = "{