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soc/amd/common: Save the UMA settings from AGESA 

Save the UMA base and size settings returned by AGESA
in amdinitpost();

Change-Id: Id96cc65582118ad41d397b1a600cab1615676a55
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marc Jones 2018-02-19 13:34:31 -07:00 committed by Martin Roth
parent ab2618d488
commit 932b5bdb6d
1 changed files with 12 additions and 4 deletions
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16
src/soc/amd/common/block/pi/agesawrapper.c
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@ -26,6 +26,7 @@
#include <amdblocks/s3_resume.h>
#include <amdblocks/agesawrapper.h>
#include <amdblocks/BiosCallOuts.h>
#include <soc/southbridge.h>
void __attribute__((weak)) SetMemParams(AMD_POST_PARAMS *PostParams) {}
void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {}
@ -202,17 +203,24 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
timestamp_add_now(TS_AGESA_INIT_POST_DONE);
/*
* If UMA is enabled we currently have it below TOP_MEM as well.
* UMA may or may not be cacheable, so Sub4GCacheTop could be
* higher than UmaBase. With UMA_NONE we see UmaBase==0.
* AGESA passes back the base and size of UMA. This is the only
* opportunity to get and save these settings to be used in resource
* allocation. We also need to allocate the top of low memory.
* If UMA is below 4GiB, UMA base is the top of low memory, otherwise
* Sub4GCachetop is the top of low memory.
* With UMA_NONE we see UmaBase==0.
*/
uintptr_t top;
if (PostParams->MemConfig.UmaBase)
if (PostParams->MemConfig.UmaBase &&
(PostParams->MemConfig.UmaBase < ((4ull * GiB) >> 16)))
top = PostParams->MemConfig.UmaBase << 16;
else
top = PostParams->MemConfig.Sub4GCacheTop;
backup_top_of_low_cacheable(top);
save_uma_size(PostParams->MemConfig.UmaSize * 64 * KiB);
save_uma_base((u64)PostParams->MemConfig.UmaBase * 64 * KiB);
print_init_post_settings(PostParams);
if (status != AGESA_SUCCESS)