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soc/alderlake: Add ADL-S PCIe support 

Extend the code to support ADL-S PCIe Root Ports.
Based on DOC #619362 and #619501.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibb57ad5b11684c0079e384d9a6ba5c10905c1a23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63654
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2022-04-15 18:15:44 +02:00
parent f422ed898d
commit 933a44b80d
3 changed files with 82 additions and 0 deletions
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25
src/soc/intel/alderlake/chip.c
View File

@ -73,9 +73,15 @@ const char *soc_acpi_name(const struct device *dev)
switch (dev->path.pci.devfn) { switch (dev->path.pci.devfn) {
case SA_DEVFN_ROOT: return "MCHC"; case SA_DEVFN_ROOT: return "MCHC";
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
case SA_DEVFN_CPU_PCIE1_0: return "PEG1";
case SA_DEVFN_CPU_PCIE1_1: return "PEG2";
case SA_DEVFN_CPU_PCIE6_0: return "PEG0";
#else
case SA_DEVFN_CPU_PCIE1_0: return "PEG2"; case SA_DEVFN_CPU_PCIE1_0: return "PEG2";
case SA_DEVFN_CPU_PCIE6_0: return "PEG0"; case SA_DEVFN_CPU_PCIE6_0: return "PEG0";
case SA_DEVFN_CPU_PCIE6_2: return "PEG1"; case SA_DEVFN_CPU_PCIE6_2: return "PEG1";
#endif
case SA_DEVFN_IGD: return "GFX0"; case SA_DEVFN_IGD: return "GFX0";
case SA_DEVFN_TCSS_XHCI: return "TXHC"; case SA_DEVFN_TCSS_XHCI: return "TXHC";
case SA_DEVFN_TCSS_XDCI: return "TXDC"; case SA_DEVFN_TCSS_XDCI: return "TXDC";
@ -110,6 +116,25 @@ const char *soc_acpi_name(const struct device *dev)
case PCH_DEVFN_PCIE10: return "RP10"; case PCH_DEVFN_PCIE10: return "RP10";
case PCH_DEVFN_PCIE11: return "RP11"; case PCH_DEVFN_PCIE11: return "RP11";
case PCH_DEVFN_PCIE12: return "RP12"; case PCH_DEVFN_PCIE12: return "RP12";
case PCH_DEVFN_PCIE13: return "RP13";
case PCH_DEVFN_PCIE14: return "RP14";
case PCH_DEVFN_PCIE15: return "RP15";
case PCH_DEVFN_PCIE16: return "RP16";
case PCH_DEVFN_PCIE17: return "RP17";
case PCH_DEVFN_PCIE18: return "RP18";
case PCH_DEVFN_PCIE19: return "RP19";
case PCH_DEVFN_PCIE20: return "RP20";
case PCH_DEVFN_PCIE21: return "RP21";
case PCH_DEVFN_PCIE22: return "RP22";
case PCH_DEVFN_PCIE23: return "RP23";
case PCH_DEVFN_PCIE24: return "RP24";
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
/* Avoid conflicts with PCH-N eMMC */
case PCH_DEVFN_PCIE25: return "RP25";
case PCH_DEVFN_PCIE26: return "RP26";
case PCH_DEVFN_PCIE27: return "RP27";
case PCH_DEVFN_PCIE28: return "RP28";
#endif
case PCH_DEVFN_PMC: return "PMC"; case PCH_DEVFN_PMC: return "PMC";
case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART0: return "UAR0";
case PCH_DEVFN_UART1: return "UAR1"; case PCH_DEVFN_UART1: return "UAR1";

37
src/soc/intel/alderlake/include/soc/pci_devs.h
View File

@ -27,6 +27,7 @@
#define SA_DEV_SLOT_CPU_1 0x01 #define SA_DEV_SLOT_CPU_1 0x01
#define SA_DEVFN_CPU_PCIE1_0 PCI_DEVFN(SA_DEV_SLOT_CPU_1, 0) #define SA_DEVFN_CPU_PCIE1_0 PCI_DEVFN(SA_DEV_SLOT_CPU_1, 0)
#define SA_DEVFN_CPU_PCIE1_1 PCI_DEVFN(SA_DEV_SLOT_CPU_1, 1)
#define SA_DEV_SLOT_IGD 0x02 #define SA_DEV_SLOT_IGD 0x02
#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
@ -195,10 +196,46 @@
#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) #define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1)
#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) #define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2)
#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) #define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3)
#define PCH_DEVFN_PCIE13 _PCH_DEVFN(PCIE_1, 4)
#define PCH_DEVFN_PCIE14 _PCH_DEVFN(PCIE_1, 5)
#define PCH_DEVFN_PCIE15 _PCH_DEVFN(PCIE_1, 6)
#define PCH_DEVFN_PCIE16 _PCH_DEVFN(PCIE_1, 7)
#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) #define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0)
#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) #define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1)
#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) #define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2)
#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) #define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3)
#define PCH_DEV_PCIE13 _PCH_DEV(PCIE_1, 4)
#define PCH_DEV_PCIE14 _PCH_DEV(PCIE_1, 5)
#define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6)
#define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7)
#define PCH_DEV_SLOT_PCIE_2 0x1b
#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0)
#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1)
#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2)
#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3)
#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4)
#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5)
#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6)
#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7)
#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0)
#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1)
#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2)
#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3)
#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4)
#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5)
#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6)
#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7)
#define PCH_DEV_SLOT_PCIE_3 0x1a
#define PCH_DEVFN_PCIE25 _PCH_DEVFN(PCIE_3, 0)
#define PCH_DEVFN_PCIE26 _PCH_DEVFN(PCIE_3, 1)
#define PCH_DEVFN_PCIE27 _PCH_DEVFN(PCIE_3, 2)
#define PCH_DEVFN_PCIE28 _PCH_DEVFN(PCIE_3, 3)
#define PCH_DEV_PCIE25 _PCH_DEV(PCIE_3, 0)
#define PCH_DEV_PCIE26 _PCH_DEV(PCIE_3, 1)
#define PCH_DEV_PCIE27 _PCH_DEV(PCIE_3, 2)
#define PCH_DEV_PCIE28 _PCH_DEV(PCIE_3, 3)
#define PCH_DEV_SLOT_SIO5 0x1e #define PCH_DEV_SLOT_SIO5 0x1e
#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0) #define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0)

20
src/soc/intel/alderlake/pcie_rp.c
View File

@ -20,11 +20,22 @@ static const struct pcie_rp_group pch_m_rp_groups[] = {
{ 0 } { 0 }
}; };
static const struct pcie_rp_group pch_s_rp_groups[] = {
{ .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
{ .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 },
{ .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 },
{ .slot = PCH_DEV_SLOT_PCIE_3, .count = 4, .lcap_port_base = 1 },
{ 0 }
};
const struct pcie_rp_group *get_pch_pcie_rp_table(void) const struct pcie_rp_group *get_pch_pcie_rp_table(void)
{ {
if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)) if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M))
return pch_m_rp_groups; return pch_m_rp_groups;
if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S))
return pch_s_rp_groups;
return pch_lp_rp_groups; /* Valid for PCH-P and PCH-N */ return pch_lp_rp_groups; /* Valid for PCH-P and PCH-N */
} }
@ -50,6 +61,12 @@ static const struct pcie_rp_group cpu_n_rp_groups[] = {
{ 0 } { 0 }
}; };
static const struct pcie_rp_group cpu_s_rp_groups[] = {
{ .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1, .lcap_port_base = 1 },
{ .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 2, .lcap_port_base = 1 },
{ 0 }
};
const struct pcie_rp_group *get_cpu_pcie_rp_table(void) const struct pcie_rp_group *get_cpu_pcie_rp_table(void)
{ {
if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)) if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M))
@ -58,6 +75,9 @@ const struct pcie_rp_group *get_cpu_pcie_rp_table(void)
if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)) if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_N))
return cpu_n_rp_groups; return cpu_n_rp_groups;
if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S))
return cpu_s_rp_groups;
return cpu_rp_groups; return cpu_rp_groups;
} }