diff --git a/src/soc/amd/common/BiosCallOuts.h b/src/soc/amd/common/BiosCallOuts.h
index 50931dcfb1..44564665eb 100644
--- a/src/soc/amd/common/BiosCallOuts.h
+++ b/src/soc/amd/common/BiosCallOuts.h
@@ -14,8 +14,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef CALLOUTS_AMD_AGESA_H
-#define CALLOUTS_AMD_AGESA_H
+#ifndef __CALLOUTS_AMD_AGESA_H__
+#define __CALLOUTS_AMD_AGESA_H__
 
 #include <Porting.h>
 #include <AGESA.h>
@@ -64,4 +64,4 @@ typedef struct {
 extern const BIOS_CALLOUT_STRUCT BiosCallouts[];
 extern const int BiosCalloutsLen;
 
-#endif /* CALLOUTS_AMD_AGESA_H */
+#endif /* __CALLOUTS_AMD_AGESA_H__ */
diff --git a/src/soc/amd/common/agesawrapper.h b/src/soc/amd/common/agesawrapper.h
index 97d52f7c10..b42f531352 100644
--- a/src/soc/amd/common/agesawrapper.h
+++ b/src/soc/amd/common/agesawrapper.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _AGESAWRAPPER_H_
-#define _AGESAWRAPPER_H_
+#ifndef __AGESAWRAPPER_H__
+#define __AGESAWRAPPER_H__
 
 #include <stdint.h>
 #include <Porting.h>
@@ -56,4 +56,4 @@ const void *agesawrapper_locate_module(const CHAR8 name[8]);
 
 void OemPostParams(AMD_POST_PARAMS *PostParams);
 
-#endif /* _AGESAWRAPPER_H_ */
+#endif /* __AGESAWRAPPER_H__ */
diff --git a/src/soc/amd/common/agesawrapper_call.h b/src/soc/amd/common/agesawrapper_call.h
index 64c97f6640..21a1e23d54 100644
--- a/src/soc/amd/common/agesawrapper_call.h
+++ b/src/soc/amd/common/agesawrapper_call.h
@@ -11,8 +11,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _AGESAWRAPPER_CALL_H_
-#define _AGESAWRAPPER_CALL_H_
+#ifndef __AGESAWRAPPER_CALL_H__
+#define __AGESAWRAPPER_CALL_H__
 
 #include <stdint.h>
 #include <console/console.h>
@@ -56,4 +56,4 @@ static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name)
 
 #define AGESAWRAPPER_PRE_CONSOLE(func) agesawrapper_ ## func()
 
-#endif
+#endif /* __AGESAWRAPPER_CALL_H__ */
diff --git a/src/soc/amd/common/amd_defs.h b/src/soc/amd/common/amd_defs.h
index 55db30f409..e4ce1dba22 100644
--- a/src/soc/amd/common/amd_defs.h
+++ b/src/soc/amd/common/amd_defs.h
@@ -14,8 +14,8 @@
  */
 
 
-#ifndef _AMD_SB_DEFS_H_
-#define _AMD_SB_DEFS_H_
+#ifndef __AMD_SB_DEFS_H__
+#define __AMD_SB_DEFS_H__
 
 #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000ul
 
diff --git a/src/soc/amd/common/amd_pci_util.h b/src/soc/amd/common/amd_pci_util.h
index 4789542e58..b8d48ef3e3 100644
--- a/src/soc/amd/common/amd_pci_util.h
+++ b/src/soc/amd/common/amd_pci_util.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef AMD_PCI_UTIL_H
-#define AMD_PCI_UTIL_H
+#ifndef __AMD_PCI_UTIL_H__
+#define __AMD_PCI_UTIL_H__
 
 #include <stdint.h>
 #include <amd_pci_int_defs.h>
@@ -38,4 +38,4 @@ void write_pci_int_idx(u8 index, int mode, u8 data);
 void write_pci_cfg_irqs(void);
 void write_pci_int_table(void);
 
-#endif /* AMD_PCI_UTIL_H */
+#endif /* __AMD_PCI_UTIL_H__ */
diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h
index c70c0b1032..42b9fb7178 100644
--- a/src/soc/amd/common/block/include/amdblocks/psp.h
+++ b/src/soc/amd/common/block/include/amdblocks/psp.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef AMD_PSP_H
-#define AMD_PSP_H
+#ifndef __AMD_PSP_H__
+#define __AMD_PSP_H__
 
 #include <stdint.h>
 #include <compiler.h>
@@ -94,4 +94,4 @@ struct mbox_default_buffer {	/* command-response buffer unused by command */
 /* BIOS-to-PSP functions return 0 if successful, else negative value */
 int psp_notify_dram(void);
 
-#endif /* AMD_PSP_H */
+#endif /* __AMD_PSP_H__ */
diff --git a/src/soc/amd/common/dimmSpd.h b/src/soc/amd/common/dimmSpd.h
index 75a7990c2c..cdcdb731f5 100644
--- a/src/soc/amd/common/dimmSpd.h
+++ b/src/soc/amd/common/dimmSpd.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _DIMMSPD_H_
-#define _DIMMSPD_H_
+#ifndef __DIMMSPD_H__
+#define __DIMMSPD_H__
 
 AGESA_STATUS
 AmdMemoryReadSPD(IN UINT32 Func, IN UINTN Data,
diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h
index 747c2956f1..cd3bc74d90 100644
--- a/src/soc/amd/stoneyridge/chip.h
+++ b/src/soc/amd/stoneyridge/chip.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef STONEYRIDGE_CHIP_H
-#define STONEYRIDGE_CHIP_H
+#ifndef __STONEYRIDGE_CHIP_H__
+#define __STONEYRIDGE_CHIP_H__
 
 #include <stdint.h>
 
@@ -32,4 +32,4 @@ typedef struct soc_amd_stoneyridge_config config_t;
 
 extern struct device_operations pci_domain_ops;
 
-#endif /* STONEYRIDGE_CHIP_H */
+#endif /* __STONEYRIDGE_CHIP_H__ */
diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h
index f3f60d3b61..a8e75f6327 100644
--- a/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h
+++ b/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef AMD_PCI_INT_DEFS_H
-#define AMD_PCI_INT_DEFS_H
+#ifndef __AMD_PCI_INT_DEFS_H__
+#define __AMD_PCI_INT_DEFS_H__
 
 /*
  * PIRQ and device routing - these define the index
@@ -72,4 +72,4 @@
 #define PIRQ_UART0	0x74
 #define PIRQ_UART1	0x75
 
-#endif /* AMD_PCI_INT_DEFS_H */
+#endif /* __AMD_PCI_INT_DEFS_H__ */
diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
index ab1f70b869..08bdc108cf 100644
--- a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
+++ b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef AMD_PCI_INT_TYPES_H
-#define AMD_PCI_INT_TYPES_H
+#ifndef __AMD_PCI_INT_TYPES_H__
+#define __AMD_PCI_INT_TYPES_H__
 
 const char *intr_types[] = {
 	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t",
@@ -34,4 +34,4 @@ const char *intr_types[] = {
 	[0x70] = "I2C0\t", "I2C1\t", "I2C2\t", "I2C3\t", "UART0\t", "UART1\t",
 };
 
-#endif /* AMD_PCI_INT_TYPES_H */
+#endif /* __AMD_PCI_INT_TYPES_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h
index f573b0ed81..3e58d9a0c7 100644
--- a/src/soc/amd/stoneyridge/include/soc/acpi.h
+++ b/src/soc/amd/stoneyridge/include/soc/acpi.h
@@ -15,8 +15,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_STONEYRIDGE_ACPI_H_
-#define _SOC_STONEYRIDGE_ACPI_H_
+#ifndef __SOC_STONEYRIDGE_ACPI_H__
+#define __SOC_STONEYRIDGE_ACPI_H__
 
 #include <arch/acpi.h>
 
@@ -35,4 +35,4 @@ unsigned long southbridge_write_acpi_tables(device_t device,
 
 void southbridge_inject_dsdt(device_t device);
 
-#endif	/* _SOC_STONEYRIDGE_ACPI_H_ */
+#endif /* __SOC_STONEYRIDGE_ACPI_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index c43dd2767a..c5b7c8a4d4 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _STONEYRIDGE_GPIO_H_
-#define _STONEYRIDGE_GPIO_H_
+#ifndef __STONEYRIDGE_GPIO_H__
+#define __STONEYRIDGE_GPIO_H__
 
 #include <soc/amd/common/amd_defs.h>
 #include <types.h>
@@ -129,4 +129,4 @@
 
 typedef uint32_t gpio_t;
 
-#endif	/* _STONEYRIDGE_GPIO_H_ */
+#endif /* __STONEYRIDGE_GPIO_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/imc.h b/src/soc/amd/stoneyridge/include/soc/imc.h
index a077506ff3..d61340941c 100644
--- a/src/soc/amd/stoneyridge/include/soc/imc.h
+++ b/src/soc/amd/stoneyridge/include/soc/imc.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef STONEYRIDGE_IMC_H
-#define STONEYRIDGE_IMC_H
+#ifndef __STONEYRIDGE_IMC_H__
+#define __STONEYRIDGE_IMC_H__
 
 void imc_reg_init(void);
 void enable_imc_thermal_zone(void);
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index e082a9d067..13d7d36270 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef PI_STONEYRIDGE_NORTHBRIDGE_H
-#define PI_STONEYRIDGE_NORTHBRIDGE_H
+#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__
+#define __PI_STONEYRIDGE_NORTHBRIDGE_H__
 
 #include <arch/cpu.h>
 #include <arch/io.h>
@@ -30,4 +30,4 @@ void setup_uma_memory(void);
 /* todo: remove this when postcar stage is in place */
 asmlinkage void chipset_teardown_car(void);
 
-#endif /* PI_STONEYRIDGE_NORTHBRIDGE_H */
+#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h
index b28f386ec8..68763a94de 100644
--- a/src/soc/amd/stoneyridge/include/soc/nvs.h
+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h
@@ -21,8 +21,8 @@
  *
  */
 
-#ifndef _SOC_STONEYRIDGE_NVS_H_
-#define _SOC_STONEYRIDGE_NVS_H_
+#ifndef __SOC_STONEYRIDGE_NVS_H__
+#define __SOC_STONEYRIDGE_NVS_H__
 
 #include <stdint.h>
 #include <vendorcode/google/chromeos/gnvs.h>
@@ -48,4 +48,4 @@ typedef struct global_nvs_t {
 	chromeos_acpi_t chromeos;
 } __attribute__((packed)) global_nvs_t;
 
-#endif	/* _SOC_STONEYRIDGE_NVS_H_ */
+#endif /* __SOC_STONEYRIDGE_NVS_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
index 8bea376f64..5c7f86a8c7 100644
--- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h
+++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _PI_STONEYRIDGE_PCI_DEVS_H_
-#define _PI_STONEYRIDGE_PCI_DEVS_H_
+#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__
+#define __PI_STONEYRIDGE_PCI_DEVS_H__
 
 #include <device/pci_def.h>
 #include <rules.h>
@@ -285,4 +285,4 @@
 #define SD_DEVID		0x7906
 #define SD_DEVFN		PCI_DEVFN(SD_DEV, SD_FUNC)
 
-#endif /* _PI_STONEYRIDGE_PCI_DEVS_H_ */
+#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h
index c9b19e5fc2..90a59e4743 100644
--- a/src/soc/amd/stoneyridge/include/soc/smbus.h
+++ b/src/soc/amd/stoneyridge/include/soc/smbus.h
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef STONEYRIDGE_SMBUS_H
-#define STONEYRIDGE_SMBUS_H
+#ifndef __STONEYRIDGE_SMBUS_H__
+#define __STONEYRIDGE_SMBUS_H__
 
 #include <stdint.h>
 
@@ -67,4 +67,4 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
 void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
 void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val);
 
-#endif	/* STONEYRIDGE_SMBUS_H */
+#endif /* __STONEYRIDGE_SMBUS_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h
index 193fb0ced3..46004c9a31 100644
--- a/src/soc/amd/stoneyridge/include/soc/smi.h
+++ b/src/soc/amd/stoneyridge/include/soc/smi.h
@@ -5,8 +5,8 @@
  * Subject to the GNU GPL v2, or (at your option) any later version.
  */
 
-#ifndef _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H
-#define _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H
+#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
+#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
 
 #include <arch/io.h>
 
@@ -62,4 +62,4 @@ void enable_acpi_cmd_smi(void);
 void enable_smi_generation(void);
 #endif
 
-#endif /* _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H */
+#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index de481f0eea..20edf5f4cc 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -14,8 +14,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef STONEYRIDGE_H
-#define STONEYRIDGE_H
+#ifndef __STONEYRIDGE_H__
+#define __STONEYRIDGE_H__
 
 #include <arch/io.h>
 #include <types.h>
@@ -204,4 +204,4 @@ void s3_resume_init_data(void *FchParams);
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 void bootblock_fch_early_init(void);
 
-#endif /* STONEYRIDGE_H */
+#endif /* __STONEYRIDGE_H__ */