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sb/intel/lynxpoint: Drop stale code paths 

These appear to be leftovers from old SMM relocation code.

Change-Id: I689bee55943b29990f54cb798b999940eae180bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2020-06-21 00:26:53 +03:00 committed by Patrick Georgi
parent d15183144a
commit 933f90147b
1 changed files with 0 additions and 32 deletions
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32
src/southbridge/intel/lynxpoint/smi.c
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@ -58,38 +58,6 @@ void global_smi_enable(void)
smm_southbridge_enable(PWRBTN_EN | GBL_EN);
}
static void __unused southbridge_trigger_smi(void)
{
/**
* There are several methods of raising a controlled SMI# via
* software, among them:
* - Writes to io 0xb2 (APMC)
* - Writes to the Local Apic ICR with Delivery mode SMI.
*
* Using the local APIC is a bit more tricky. According to
* AMD Family 11 Processor BKDG no destination shorthand must be
* used.
* The whole SMM initialization is quite a bit hardware specific, so
* I'm not too worried about the better of the methods at the moment
*/
/* raise an SMI interrupt */
printk(BIOS_SPEW, " ... raise SMI#\n");
apm_control(APM_CNT_NOOP_SMI);
}
static void __unused southbridge_clear_smi_status(void)
{
/* Clear SMI status */
clear_smi_status();
/* Clear PM1 status */
clear_pm1_status();
/* Set EOS bit so other SMIs can occur. */
enable_smi(EOS);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
{
/*