sb/nvidia/mcp55: Avoid confusion with PCI_ADDR()
What you see in the table are not the PCI devices that will be written to. Use a helper MCP55_DEV() to make you look twice what is actually done. Change-Id: I1349af9f734aaabb576d1370ae29a56c91569a7c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki
parent
43997b7aa3
commit
934156694f
1 changed files with 66 additions and 61 deletions
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@ -72,14 +72,19 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
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#define MCP55_CHIP_REV 3
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/* There will be implicit offsets applied, the writes below do not
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* really happen at the PCI_ADDR() this expands to.
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*/
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#define MCP55_DEV(d, f, r) PCI_ADDR(0, d, f, r)
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static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn,
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unsigned *devn, unsigned *io_base)
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{
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static const unsigned int ctrl_devport_conf[] = {
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PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
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PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
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PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE,
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MCP55_DEV(1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
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MCP55_DEV(1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
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MCP55_DEV(1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE,
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};
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int j;
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@ -94,9 +99,9 @@ static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn,
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unsigned *devn, unsigned *io_base)
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{
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static const unsigned int ctrl_devport_conf_clear[] = {
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PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
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PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
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PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0,
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MCP55_DEV(1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
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MCP55_DEV(1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
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MCP55_DEV(1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0,
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};
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int j;
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@ -174,70 +179,70 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
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RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00,
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RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000,
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RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xFFFFDCED, 0x00002002,
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RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x78), 0xFFFFFF8E, 0x00000011,
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RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x80), 0xFFFF0000, 0x00009923,
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RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x88), 0xFFFFFFFE, 0x00000000,
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RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8C), 0xFFFF0000, 0x0000007F,
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RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xDC), 0xFFFEFFFF, 0x00010000,
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RES_PCI_IO, MCP55_DEV(0, 0, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, MCP55_DEV(0, 0, 0x48), 0xFFFFDCED, 0x00002002,
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RES_PCI_IO, MCP55_DEV(0, 0, 0x78), 0xFFFFFF8E, 0x00000011,
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RES_PCI_IO, MCP55_DEV(0, 0, 0x80), 0xFFFF0000, 0x00009923,
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RES_PCI_IO, MCP55_DEV(0, 0, 0x88), 0xFFFFFFFE, 0x00000000,
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RES_PCI_IO, MCP55_DEV(0, 0, 0x8C), 0xFFFF0000, 0x0000007F,
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RES_PCI_IO, MCP55_DEV(0, 0, 0xDC), 0xFFFEFFFF, 0x00010000,
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RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFFFF7B, 0x00000084,
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RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
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RES_PCI_IO, MCP55_DEV(1, 0, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, MCP55_DEV(1, 0, 0x74), 0xFFFFFF7B, 0x00000084,
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RES_PCI_IO, MCP55_DEV(1, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
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RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xC4), 0xFFFFFFFE, 0x00000001,
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RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF0), 0x7FFFFFFD, 0x00000002,
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RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
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RES_PCI_IO, MCP55_DEV(1, 1, 0xC4), 0xFFFFFFFE, 0x00000001,
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RES_PCI_IO, MCP55_DEV(1, 1, 0xF0), 0x7FFFFFFD, 0x00000002,
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RES_PCI_IO, MCP55_DEV(1, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
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RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF,
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RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */
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RES_PCI_IO, MCP55_DEV(8, 0, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, MCP55_DEV(8, 0, 0x68), 0xFFFFFF00, 0x000000FF,
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RES_PCI_IO, MCP55_DEV(8, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */
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RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF,
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RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */
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RES_PCI_IO, MCP55_DEV(9, 0, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, MCP55_DEV(9, 0, 0x68), 0xFFFFFF00, 0x000000FF,
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RES_PCI_IO, MCP55_DEV(9, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */
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};
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static const unsigned int ctrl_conf_1_1[] = {
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RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003,
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RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001,
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RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x70), 0xFFF0FFFF, 0x00040000,
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RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xAC), 0xFFFFF0FF, 0x00000100,
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RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x7C), 0xFFFFFFEF, 0x00000000,
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RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A,
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RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000,
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RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000,
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RES_PCI_IO, MCP55_DEV(5, 0, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, MCP55_DEV(5, 0, 0x50), 0xFFFFFFFC, 0x00000003,
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RES_PCI_IO, MCP55_DEV(5, 0, 0x64), 0xFFFFFFFE, 0x00000001,
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RES_PCI_IO, MCP55_DEV(5, 0, 0x70), 0xFFF0FFFF, 0x00040000,
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RES_PCI_IO, MCP55_DEV(5, 0, 0xAC), 0xFFFFF0FF, 0x00000100,
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RES_PCI_IO, MCP55_DEV(5, 0, 0x7C), 0xFFFFFFEF, 0x00000000,
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RES_PCI_IO, MCP55_DEV(5, 0, 0xC8), 0xFF00FF00, 0x000A000A,
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RES_PCI_IO, MCP55_DEV(5, 0, 0xD0), 0xF0FFFFFF, 0x03000000,
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RES_PCI_IO, MCP55_DEV(5, 0, 0xE0), 0xF0FFFFFF, 0x03000000,
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};
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static const unsigned int ctrl_conf_mcp55_only[] = {
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RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000,
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RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000,
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RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE8), 0xFFA9C8FF, 0x00003000,
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RES_PCI_IO, MCP55_DEV(1, 1, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, MCP55_DEV(1, 1, 0xE0), 0xFFFFFEFF, 0x00000000,
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RES_PCI_IO, MCP55_DEV(1, 1, 0xE4), 0xFFFFFFFB, 0x00000000,
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RES_PCI_IO, MCP55_DEV(1, 1, 0xE8), 0xFFA9C8FF, 0x00003000,
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RES_PCI_IO, PCI_ADDR(0, 4, 0, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, PCI_ADDR(0, 4, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
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RES_PCI_IO, MCP55_DEV(4, 0, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, MCP55_DEV(4, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
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RES_PCI_IO, PCI_ADDR(0, 2, 0, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, MCP55_DEV(2, 0, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xF87FFFFF, 0x05000000,
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RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xFFC07FFF, 0x00360000,
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RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0xFE00D03F, 0x013F2C00,
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RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xFFF7FFFF, 0x00080000,
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RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7C), 0xFFFFF00F, 0x00000570,
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RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
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RES_PCI_IO, MCP55_DEV(2, 1, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, MCP55_DEV(2, 1, 0x64), 0xF87FFFFF, 0x05000000,
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RES_PCI_IO, MCP55_DEV(2, 1, 0x78), 0xFFC07FFF, 0x00360000,
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RES_PCI_IO, MCP55_DEV(2, 1, 0x68), 0xFE00D03F, 0x013F2C00,
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RES_PCI_IO, MCP55_DEV(2, 1, 0x70), 0xFFF7FFFF, 0x00080000,
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RES_PCI_IO, MCP55_DEV(2, 1, 0x7C), 0xFFFFF00F, 0x00000570,
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RES_PCI_IO, MCP55_DEV(2, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
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RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x04), 0xFFFFFEFB, 0x00000104,
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RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000,
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RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x40), 0x00C8FFFF, 0x07330000,
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RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x48), 0xFFFFFFF8, 0x00000005,
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RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x4C), 0xFE02FFFF, 0x004C0000,
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RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
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RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
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RES_PCI_IO, MCP55_DEV(6, 0, 0x04), 0xFFFFFEFB, 0x00000104,
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RES_PCI_IO, MCP55_DEV(6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000,
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RES_PCI_IO, MCP55_DEV(6, 0, 0x40), 0x00C8FFFF, 0x07330000,
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RES_PCI_IO, MCP55_DEV(6, 0, 0x48), 0xFFFFFFF8, 0x00000005,
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RES_PCI_IO, MCP55_DEV(6, 0, 0x4C), 0xFE02FFFF, 0x004C0000,
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RES_PCI_IO, MCP55_DEV(6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
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RES_PCI_IO, MCP55_DEV(6, 0, 0xC0), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, MCP55_DEV(6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
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#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
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/*
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* Avoid crash (complete with severe memory corruption!) during initial CAR boot
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@ -247,11 +252,11 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
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* required to fix this is non-negligible and of unknown real-world benefit
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*/
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#else
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RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
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RES_PCI_IO, MCP55_DEV(1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
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#endif
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#if IS_ENABLED(CONFIG_MCP55_USE_AZA)
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RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
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RES_PCI_IO, MCP55_DEV(6, 1, 0x40), 0x00000000, 0xCB8410DE,
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#endif
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@ -277,15 +282,15 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
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static const unsigned int ctrl_conf_2[] = {
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/* I didn't put PCI-E related stuff here. */
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RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0,
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RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000,
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RES_PCI_IO, MCP55_DEV(0, 0, 0x74), 0xFFFFF00F, 0x000009D0,
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RES_PCI_IO, MCP55_DEV(1, 0, 0x74), 0xFFFF7FFF, 0x00008000,
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RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000,
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RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
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#if IS_ENABLED(CONFIG_MCP55_USE_NIC)
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RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20),
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RES_PCI_IO, MCP55_DEV(1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20),
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
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